/* Date Stamp: 8/23/2014 */

#ifndef IIO_RAS_h
#define IIO_RAS_h

#include "DataTypes.h"

/* Device and Function specifications:                                        */
/* For all target CPUs:                                                       */
/* IIO_RAS_DEV 5                                                              */
/* IIO_RAS_FUN 2                                                              */

/* VID_IIO_RAS_REG supported on:                                              */
/*       IVT_EP (0x2002A000)                                                  */
/*       IVT_EX (0x2002A000)                                                  */
/*       HSX (0x2002A000)                                                     */
/*       BDX (0x2002A000)                                                     */
/* Register default value:              0x8086                                */
#define VID_IIO_RAS_REG 0x09022000
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x000
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RO, default = 16'b1000000010000110 
       The value is assigned by PCI-SIG to Intel.
     */
  } Bits;
  UINT16 Data;
} VID_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* DID_IIO_RAS_REG supported on:                                              */
/*       IVT_EP (0x2002A002)                                                  */
/*       IVT_EX (0x2002A002)                                                  */
/*       HSX (0x2002A002)                                                     */
/*       BDX (0x2002A002)                                                     */
/* Register default value on IVT_EP:    0x0E2A                                */
/* Register default value on IVT_EX:    0x0E2A                                */
/* Register default value on HSX:       0x2F2A                                */
/* Register default value on BDX:       0x6F2A                                */
#define DID_IIO_RAS_REG 0x09022002
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x002
 */
typedef union {
  struct {
    UINT16 device_identification_number : 16;
    /* device_identification_number - Bits[15:0], RO, default = 16'b0110111100101010 
       Device ID values vary from function to function. Bits 15:8 are equal to 0x6F for 
       the processor. The following list is a breakdown of the function groups. 
       0x6F00 - 0x6F1F : PCI Express and DMI ports
       0x6F20 - 0x6F3F : IO Features (Intel QuickData Technology, APIC, VT, RAS, Intel 
       TXT) 
       0x6F40 - 0x6F5F : Performance Monitors
       0x6F60 - 0x6F7F : DFX
       0x6F80 - 0x6F9F : Intel QPI
       0x6FA0 - 0x6FBF : Home Agent/Memory Controller
       0x6FC0 - 0x6FDF : Power Management
       0x6FE0 - 0x6FFF : Cbo/Ring
       
       Default value may vary based on bus, device, and function of this CSR location.
     */
  } Bits;
  UINT16 Data;
} DID_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* PCICMD_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x2002A004)                                                  */
/*       IVT_EX (0x2002A004)                                                  */
/*       HSX (0x2002A004)                                                     */
/*       BDX (0x2002A004)                                                     */
/* Register default value:              0x0000                                */
#define PCICMD_IIO_RAS_REG 0x09022004
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x004
 */
typedef union {
  struct {
    UINT16 io_space_enable : 1;
    /* io_space_enable - Bits[0:0], RO, default = 1'b0 
       Hardwired to 0 since these devices don't decode any IO BARs
     */
    UINT16 memory_space_enable : 1;
    /* memory_space_enable - Bits[1:1], RO, default = 1'b0 
       Hardwired to 0 since these devices don't decode any memory BARs
     */
    UINT16 bus_master_enable : 1;
    /* bus_master_enable - Bits[2:2], RO, default = 1'b0 
       Hardwired to 0 since these devices don't generate any transactions
     */
    UINT16 special_cycle_enable : 1;
    /* special_cycle_enable - Bits[3:3], RO, default = 1'b0 
       Not applicable. Hardwired to 0.
     */
    UINT16 memory_write_and_invalidate_enable : 1;
    /* memory_write_and_invalidate_enable - Bits[4:4], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 vga_palette_snoop_enable : 1;
    /* vga_palette_snoop_enable - Bits[5:5], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 parity_error_response : 1;
    /* parity_error_response - Bits[6:6], RO, default = 1'b0 
       This bit has no impact on error reporting from these devices
     */
    UINT16 idsel_stepping_wait_cycle_control : 1;
    /* idsel_stepping_wait_cycle_control - Bits[7:7], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 serr_enable : 1;
    /* serr_enable - Bits[8:8], RO, default = 1'b0 
       This bit has no impact on error reporting from these devices
     */
    UINT16 fast_back_to_back_enable : 1;
    /* fast_back_to_back_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to PCI Express and is hardwired to 0
     */
    UINT16 intx_disable : 1;
    /* intx_disable - Bits[10:10], RO, default = 1'b0 
       N/A for these devices
     */
    UINT16 rsvd : 5;
    /* rsvd - Bits[15:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCICMD_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* PCISTS_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x2002A006)                                                  */
/*       IVT_EX (0x2002A006)                                                  */
/*       HSX (0x2002A006)                                                     */
/*       BDX (0x2002A006)                                                     */
/* Register default value:              0x0010                                */
#define PCISTS_IIO_RAS_REG 0x09022006
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x006
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intx_status : 1;
    /* intx_status - Bits[3:3], RO, default = 1'b0 
       Hardwired to 0
     */
    UINT16 capabilities_list : 1;
    /* capabilities_list - Bits[4:4], RO, default = 1'b1 
       This bit indicates the presence of a capabilities list structure
     */
    UINT16 pci66mhz_capable : 1;
    /* pci66mhz_capable - Bits[5:5], RO, default = 1'b0 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 fast_back_to_back : 1;
    /* fast_back_to_back - Bits[7:7], RO, default = 1'b0 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 master_data_parity_error : 1;
    /* master_data_parity_error - Bits[8:8], RO, default = 1'b0 
       Hardwired to 0
     */
    UINT16 devsel_timing : 2;
    /* devsel_timing - Bits[10:9], RO, default = 2'b00 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 signaled_target_abort : 1;
    /* signaled_target_abort - Bits[11:11], RO, default = 1'b0 
       Hardwired to 0
     */
    UINT16 received_target_abort : 1;
    /* received_target_abort - Bits[12:12], RO, default = 1'b0 
       Hardwired to 0
     */
    UINT16 received_master_abort : 1;
    /* received_master_abort - Bits[13:13], RO, default = 1'b0 
       Hardwired to 0
     */
    UINT16 signaled_system_error : 1;
    /* signaled_system_error - Bits[14:14], RO, default = 1'b0 
       Hardwired to 0
     */
    UINT16 detected_parity_error : 1;
    /* detected_parity_error - Bits[15:15], RO, default = 1'b0 
       This bit is set when the device receives a packet on the primary side with an 
       uncorrectable data error (including a packet with poison bit set) or an 
       uncorrectable address/control parity error. The setting of this bit is 
       regardless of the Parity Error Response bit (PERRE) in the PCICMD register. 
       R2PCIe will never set this bit. 
     */
  } Bits;
  UINT16 Data;
} PCISTS_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* RID_IIO_RAS_REG supported on:                                              */
/*       IVT_EP (0x1002A008)                                                  */
/*       IVT_EX (0x1002A008)                                                  */
/*       HSX (0x1002A008)                                                     */
/*       BDX (0x1002A008)                                                     */
/* Register default value:              0x00                                  */
#define RID_IIO_RAS_REG 0x09021008
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * "PCIe header Revision ID register"
 */
typedef union {
  struct {
    UINT8 revision_id : 8;
    /* revision_id - Bits[7:0], ROS_V, default = 8'b00000000 
       Reflects the Uncore Revision ID after reset.
       Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
       register in the processor uncore. 
       
     */
  } Bits;
  UINT8 Data;
} RID_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* CCR_N0_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x1002A009)                                                  */
/*       IVT_EX (0x1002A009)                                                  */
/*       HSX (0x1002A009)                                                     */
/*       BDX (0x1002A009)                                                     */
/* Register default value:              0x00                                  */
#define CCR_N0_IIO_RAS_REG 0x09021009


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT8 register_level_programming_interface : 8;
    /* register_level_programming_interface - Bits[7:0], RO_V, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CCR_N0_IIO_RAS_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CCR_N1_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x2002A00A)                                                  */
/*       IVT_EX (0x2002A00A)                                                  */
/*       HSX (0x2002A00A)                                                     */
/*       BDX (0x2002A00A)                                                     */
/* Register default value:              0x0880                                */
#define CCR_N1_IIO_RAS_REG 0x0902200A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT16 sub_class : 8;
    /* sub_class - Bits[7:0], RO_V, default = 8'b10000000 
       The value changes dependent upon the dev/func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h80 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h01. 
                 dev-0x0 through 0x7 (return 0x4, d0f0 return 0x0 under default 
       settings) 
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
    UINT16 base_class : 8;
    /* base_class - Bits[15:8], RO_V, default = 8'b00001000 
       The value changes dependent upon the dev-func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h08 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h11. 
                 dev-0x0 through 0x7 (return 0x6)
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
  } Bits;
  UINT16 Data;
} CCR_N1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* CLSR_IIO_RAS_REG supported on:                                             */
/*       IVT_EP (0x1002A00C)                                                  */
/*       IVT_EX (0x1002A00C)                                                  */
/*       HSX (0x1002A00C)                                                     */
/*       BDX (0x1002A00C)                                                     */
/* Register default value:              0x00                                  */
#define CLSR_IIO_RAS_REG 0x0902100C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x00c
 */
typedef union {
  struct {
    UINT8 cacheline_size : 8;
    /* cacheline_size - Bits[7:0], RW, default = 8'b00000000 
       This register is set as RW for compatibility reasons only. Cacheline size for 
       processor is always 64B. 
     */
  } Bits;
  UINT8 Data;
} CLSR_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* HDR_IIO_RAS_REG supported on:                                              */
/*       IVT_EP (0x1002A00E)                                                  */
/*       IVT_EX (0x1002A00E)                                                  */
/*       HSX (0x1002A00E)                                                     */
/*       BDX (0x1002A00E)                                                     */
/* Register default value:              0x80                                  */
#define HDR_IIO_RAS_REG 0x0902100E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x00e
 */
typedef union {
  struct {
    UINT8 configuration_layout : 7;
    /* configuration_layout - Bits[6:0], RO, default = 7'b0000000 
       This field identifies the format of the configuration header layout. It is Type 
       0 for all these devices. The default is 00h, indicating a 'endpoint device'. 
     */
    UINT8 multi_function_device : 1;
    /* multi_function_device - Bits[7:7], RO, default = 1'b1 
       This bit defaults to 1b since all these devices are multi-function
     */
  } Bits;
  UINT8 Data;
} HDR_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* SVID_IIO_RAS_REG supported on:                                             */
/*       IVT_EP (0x2002A02C)                                                  */
/*       IVT_EX (0x2002A02C)                                                  */
/*       HSX (0x2002A02C)                                                     */
/*       BDX (0x2002A02C)                                                     */
/* Register default value:              0x0000                                */
#define SVID_IIO_RAS_REG 0x0902202C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x02c
 */
typedef union {
  struct {
    UINT16 subsystem_vendor_identification_number : 16;
    /* subsystem_vendor_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       The default value specifies Intel but can be set to any value once after reset.
     */
  } Bits;
  UINT16 Data;
} SVID_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* SDID_IIO_RAS_REG supported on:                                             */
/*       IVT_EP (0x2002A02E)                                                  */
/*       IVT_EX (0x2002A02E)                                                  */
/*       HSX (0x2002A02E)                                                     */
/*       BDX (0x2002A02E)                                                     */
/* Register default value:              0x0000                                */
#define SDID_IIO_RAS_REG 0x0902202E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x02e
 */
typedef union {
  struct {
    UINT16 subsystem_device_identification_number : 16;
    /* subsystem_device_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       Assigned by the subsystem vendor to uniquely identify the subsystem
     */
  } Bits;
  UINT16 Data;
} SDID_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* CAPPTR_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x1002A034)                                                  */
/*       IVT_EX (0x1002A034)                                                  */
/*       HSX (0x1002A034)                                                     */
/*       BDX (0x1002A034)                                                     */
/* Register default value:              0x40                                  */
#define CAPPTR_IIO_RAS_REG 0x09021034
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x034
 */
typedef union {
  struct {
    UINT8 capability_pointer : 8;
    /* capability_pointer - Bits[7:0], RO, default = 8'b01000000 
       Points to the first capability structure for the device which is the PCIe 
       capability. 
     */
  } Bits;
  UINT8 Data;
} CAPPTR_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* INTL_IIO_RAS_REG supported on:                                             */
/*       IVT_EP (0x1002A03C)                                                  */
/*       IVT_EX (0x1002A03C)                                                  */
/*       HSX (0x1002A03C)                                                     */
/*       BDX (0x1002A03C)                                                     */
/* Register default value:              0x00                                  */
#define INTL_IIO_RAS_REG 0x0902103C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x03c
 */
typedef union {
  struct {
    UINT8 interrupt_line : 8;
    /* interrupt_line - Bits[7:0], RO, default = 8'b00000000 
       N/A for these devices
     */
  } Bits;
  UINT8 Data;
} INTL_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* INTPIN_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x1002A03D)                                                  */
/*       IVT_EX (0x1002A03D)                                                  */
/*       HSX (0x1002A03D)                                                     */
/*       BDX (0x1002A03D)                                                     */
/* Register default value:              0x00                                  */
#define INTPIN_IIO_RAS_REG 0x0902103D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x03d
 */
typedef union {
  struct {
    UINT8 interrupt_pin : 8;
    /* interrupt_pin - Bits[7:0], RO, default = 8'b00000000 
       N/A since these devices do not generate any interrupt on their own
     */
  } Bits;
  UINT8 Data;
} INTPIN_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* PXPCAPID_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x1002A040)                                                  */
/*       IVT_EX (0x1002A040)                                                  */
/*       HSX (0x1002A040)                                                     */
/*       BDX (0x1002A040)                                                     */
/* Register default value:              0x10                                  */
#define PXPCAPID_IIO_RAS_REG 0x09021040
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x040
 */
typedef union {
  struct {
    UINT8 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00010000 
       Provides the PCI Express capability ID assigned by PCI-SIG.
     */
  } Bits;
  UINT8 Data;
} PXPCAPID_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* PXPNXTPTR_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x1002A041)                                                  */
/*       IVT_EX (0x1002A041)                                                  */
/*       HSX (0x1002A041)                                                     */
/*       BDX (0x1002A041)                                                     */
/* Register default value:              0x00                                  */
#define PXPNXTPTR_IIO_RAS_REG 0x09021041
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x041
 */
typedef union {
  struct {
    UINT8 next_ptr : 8;
    /* next_ptr - Bits[7:0], RO, default = 8'b00000000 
       This field is set to the PCI PM capability.
     */
  } Bits;
  UINT8 Data;
} PXPNXTPTR_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* PXPCAP_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x2002A042)                                                  */
/*       IVT_EX (0x2002A042)                                                  */
/*       HSX (0x2002A042)                                                     */
/*       BDX (0x2002A042)                                                     */
/* Register default value:              0x0092                                */
#define PXPCAP_IIO_RAS_REG 0x09022042
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x042
 */
typedef union {
  struct {
    UINT16 capability_version : 4;
    /* capability_version - Bits[3:0], RO, default = 4'b0010 
       This field identifies the version of the PCI Express capability structure. Set 
       to 2h for PCI Express and DMA devices for compliance with the extended base 
       registers. 
     */
    UINT16 device_port_type : 4;
    /* device_port_type - Bits[7:4], RO, default = 4'b1001 
       This field identifies the type of device. It is set to for the DMA to indicate 
       root complex integrated endpoint device. 
     */
    UINT16 slot_implemented_n_a : 1;
    /* slot_implemented_n_a - Bits[8:8], RO, default = 1'b0  */
    UINT16 interrupt_message_number_n_a : 5;
    /* interrupt_message_number_n_a - Bits[13:9], RO, default = 5'b00000  */
    UINT16 rsvd : 2;
    /* rsvd - Bits[15:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PXPCAP_IIO_RAS_STRUCT;
#endif /* ASM_INC */




















/* IRPPERRSV_N0_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A080)                                                  */
/*       IVT_EX (0x4002A080)                                                  */
/*       HSX (0x4002A080)                                                     */
/*       BDX (0x4002A080)                                                     */
/* Register default value:              0x28200150                            */
#define IRPPERRSV_N0_IIO_RAS_REG 0x09024080
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Severity.
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 2;
    /* rsvd_0 - Bits[1:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error : 2;
    /* wrcache_correcc_error - Bits[3:2], RWS, default = 2'b00 
       (Error Code 0xB4)
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
     */
    UINT32 protocol_rcvd_poison : 2;
    /* protocol_rcvd_poison - Bits[5:4], RWS, default = 2'b01 
       (Error Code 0xC1)
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
     */
    UINT32 wrcache_uncecc_error : 2;
    /* wrcache_uncecc_error - Bits[7:6], RWS, default = 2'b01 
       (Error Code 0xC2)
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
     */
    UINT32 csr_acc_32b_unaligned : 2;
    /* csr_acc_32b_unaligned - Bits[9:8], RWS, default = 2'b01 
       (Error Code 0xC3)
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
       Note: Inband misaligned to or sideband/PECI misaligned to configuration 
       registers will not be logged by this registers. 
     */
    UINT32 rsvd_10 : 10;
    /* rsvd_10 - Bits[19:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 2;
    /* protocol_rcvd_unexprsp - Bits[21:20], RWS, default = 2'b10 
       (Error Code 0xD7)
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
     */
    UINT32 rsvd_22 : 4;
    /* rsvd_22 - Bits[25:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 2;
    /* protocol_qt_overflow_underflow - Bits[27:26], RWS, default = 2'b10 
       (Error Code 0xDA)
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
       
     */
    UINT32 protocol_parity_error : 2;
    /* protocol_parity_error - Bits[29:28], RWS, default = 2'b10 
       (Error Code 0xDB)
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
     */
    UINT32 rsvd_30 : 2;
    /* rsvd_30 - Bits[31:30], n/a, default = n/a 
       This field was split. It's value spans this field and the field of similar name 
       in the next/preceding struct. 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPPERRSV_N0_IIO_RAS_STRUCT;
#endif /* ASM_INC */




/* IIOERRSV_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A08C)                                                  */
/*       IVT_EX (0x4002A08C)                                                  */
/*       HSX (0x4002A08C)                                                     */
/*       BDX (0x4002A08C)                                                     */
/* Register default value on IVT_EP:    0x00001565                            */
/* Register default value on IVT_EX:    0x00001565                            */
/* Register default value on HSX:       0x00001569                            */
/* Register default value on BDX:       0x00001569                            */
#define IIOERRSV_IIO_RAS_REG 0x0902408C


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IIO Core Error Severity.
 * This register associates the detected IIO internal core errors to an error 
 * severity level. An individual error is reported with the corresponding severity 
 * in this register. Software can program the error severity to one of the three 
 * severities supported by IIO. This register is sticky and can only be reset by 
 * PWRGOOD. 
 */
typedef union {
  struct {
    UINT32 c7_multicast_target_error : 2;
    /* c7_multicast_target_error - Bits[1:0], RWS_L, default = 2'b01 
       Multicast target error, indicating a MCAST transaction has targeted more than 
       the number of groups supported. 
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
     */
    UINT32 rsvd_2 : 6;
    UINT32 c4_master_abort_address_error : 2;
    /* c4_master_abort_address_error - Bits[9:8], RWS_L, default = 2'b01 
       Master Abort Error Severity
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
     */
    UINT32 c5_completor_abort_address_error : 2;
    /* c5_completor_abort_address_error - Bits[11:10], RWS_L, default = 2'b01 
       Completer Abort Error Severity
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
     */
    UINT32 c6 : 2;
    /* c6 - Bits[13:12], RWS_L, default = 2'b01 
       C6 Overflow/Underflow Error Severity
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
     */
    UINT32 rsvd : 18;
    /* rsvd - Bits[31:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIOERRSV_IIO_RAS_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* MIERRSV_IIO_RAS_REG supported on:                                          */
/*       IVT_EP (0x4002A090)                                                  */
/*       IVT_EX (0x4002A090)                                                  */
/*       HSX (0x4002A090)                                                     */
/*       BDX (0x4002A090)                                                     */
/* Register default value:              0x00000000                            */
#define MIERRSV_IIO_RAS_REG 0x09024090
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Error Severity.
 */
typedef union {
  struct {
    UINT32 cfg_reg_par : 2;
    /* cfg_reg_par - Bits[1:0], RWS, default = 2'b00  */
    UINT32 smbus_port_sts : 2;
    /* smbus_port_sts - Bits[3:2], RWS, default = 2'b00 
       There is no SMBus, so this is unused.
     */
    UINT32 jtag_tap_sts : 2;
    /* jtag_tap_sts - Bits[5:4], RWS, default = 2'b00  */
    UINT32 vpp_err_sts : 2;
    /* vpp_err_sts - Bits[7:6], RWS, default = 2'b00 
       VPP Port Error Status Severity.
       00: Error Severity Level 0 (Correctable)
       01: Error Severity Level 1 (Recoverable)
       10: Error Severity Level 2 (Fatal)
       11: Reserved
       It is recommended to program this bit to 1.
     */
    UINT32 rsvd_8 : 2;
    UINT32 rsvd : 22;
    /* rsvd - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MIERRSV_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* PCIERRSV_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A094)                                                  */
/*       IVT_EX (0x4002A094)                                                  */
/*       HSX (0x4002A094)                                                     */
/*       BDX (0x4002A094)                                                     */
/* Register default value:              0x00000024                            */
#define PCIERRSV_IIO_RAS_REG 0x09024094
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * PCIe* Error Severity Map.
 * This register allows remapping of the PCI-E errors to the IIO error severity.
 */
typedef union {
  struct {
    UINT32 pciecorerr_map : 2;
    /* pciecorerr_map - Bits[1:0], RWS, default = 2'b00 
       PCI-E Correctable Error Severity Map
       10: Map this PCI-E error type to Error Severity 2
       01: Map this PCI-E error type to Error Severity 1
       00: Map this PCI-E error type to Error Severity 0
     */
    UINT32 pcienonfaterr_map : 2;
    /* pcienonfaterr_map - Bits[3:2], RWS, default = 2'b01 
       PCI-E Non-Fatal Error Severity Map
       10: Map this PCI-E error type to Error Severity 2
       01: Map this PCI-E error type to Error Severity 1
       00: Map this PCI-E error type to Error Severity 0
     */
    UINT32 pciefaterr_map : 2;
    /* pciefaterr_map - Bits[5:4], RWS, default = 2'b10 
       PCI-E Fatal Error Severity Map
       10: Map this PCI-E error type to Error Severity 2
       01: Map this PCI-E error type to Error Severity 1
       00: Map this PCI-E error type to Error Severity 0
     */
    UINT32 rsvd : 26;
    /* rsvd - Bits[31:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PCIERRSV_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* SYSMAP_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x4002A09C)                                                  */
/*       IVT_EX (0x4002A09C)                                                  */
/*       HSX (0x4002A09C)                                                     */
/*       BDX (0x4002A09C)                                                     */
/* Register default value:              0x00000120                            */
#define SYSMAP_IIO_RAS_REG 0x0902409C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * System Error Event map.
 * This register maps the error severity detected by the IIO to on of the system 
 * events. When an error is detected by the IIO, its corresponding error severity 
 * determines which system event to generate according to this register. 
 */
typedef union {
  struct {
    UINT32 sev0_map : 3;
    /* sev0_map - Bits[2:0], RWS, default = 3'b000 
       Severity 0 Error Map
       010: Generate NMI
       001: Generate SMI/PMI
       000: No inband message
       Others: Reserved
     */
    UINT32 rsvd_3 : 1;
    /* rsvd_3 - Bits[3:3], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 sev1_map : 3;
    /* sev1_map - Bits[6:4], RWS, default = 3'b010 
       Severity 1 Error Map
       010: Generate NMI
       001: Generate SMI/PMI
       000: No inband message
       Others: Reserved
     */
    UINT32 rsvd_7 : 1;
    /* rsvd_7 - Bits[7:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 sev2_map : 3;
    /* sev2_map - Bits[10:8], RWS, default = 3'b001 
       Severity 2 Error Map
       010: Generate NMI
       001: Generate SMI/PMI
       000: No inband message
       Others: Reserved
     */
    UINT32 rsvd_11 : 21;
    /* rsvd_11 - Bits[31:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} SYSMAP_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* VIRAL_IIO_RAS_REG supported on:                                            */
/*       IVT_EP (0x4002A0A0)                                                  */
/*       IVT_EX (0x4002A0A0)                                                  */
/*       HSX (0x4002A0A0)                                                     */
/*       BDX (0x4002A0A0)                                                     */
/* Register default value:              0x00000000                            */
#define VIRAL_IIO_RAS_REG 0x090240A0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * This register provides the option to generate viral alert upon the detection of 
 * fatal error. 
 * Bit 0 and Bit 2 must be set to 1 to enable viral.
 * Bit 1 must be set to 1 IF and ONLY IF BIOS also enables  IOMCA in Viral mode. If 
 * IOMCA is disabled, then leave the bit at default of 0. 
 * This register is supported in the EX processor only.
 */
typedef union {
  struct {
    UINT32 iio_fatal_viral_alert_enable : 1;
    /* iio_fatal_viral_alert_enable - Bits[0:0], RW, default = 1'b0 
       Enables IIO viral alert.
     */
    UINT32 iio_signal_global_fatal : 1;
    /* iio_signal_global_fatal - Bits[1:1], RW, default = 1'b0 
       Enables IIO to signal Global Fatal for an internal fatal error.
       When in Viral mode and IOMCA is enabled, this will result in signaling CATERR# 
       when IIO detects an internal fatal error. 
       Note that CATERR# assertion in this case will be in addition to assertion of IIO 
       ERRx# pin. 
     */
    UINT32 iio_global_viral_mask : 1;
    /* iio_global_viral_mask - Bits[2:2], RW, default = 1'b0 
       0: IIO Viral State assertion will NOT cause IIO hardware packet containment.
       1: IIO Viral State assertion will cause IIO hardware packet containment.
     */
    UINT32 generate_viral_alert : 1;
    /* generate_viral_alert - Bits[3:3], RW_L, default = 1'b0 
       Debug mode to generate a viral alert when viral is enabled.
     */
    UINT32 rsvd : 26;
    /* rsvd - Bits[29:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 iio_viral_status : 1;
    /* iio_viral_status - Bits[30:30], RW1CS, default = 1'b0 
       Indicates the IIO cluster had gone to viral. This bit has no effect on hardware 
       and does not indicate the IIO is currently in the viral state. This bit is 
       persistent through warm reset (sticky), even though the viral state is not. 
     */
    UINT32 iio_viral_state : 1;
    /* iio_viral_state - Bits[31:31], RW1C, default = 1'b0 
       Indicates the IIO cluster is in a viral state. When set, all outbound requests 
       are master aborted, all inbound requests are master aborted. This includes 
       traffic to and from the DMI port, except the Reset_Warn message, which will be 
       auto-completed by the DMI port. 
       If cleared by software by setting a 1, the IIO cluster will exit the viral 
       state. This state bit is cleared by warm reset. 
     */
  } Bits;
  UINT32 Data;
} VIRAL_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* ERRPINCTL_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A0A4)                                                  */
/*       IVT_EX (0x4002A0A4)                                                  */
/*       HSX (0x4002A0A4)                                                     */
/*       BDX (0x4002A0A4)                                                     */
/* Register default value:              0x00000000                            */
#define ERRPINCTL_IIO_RAS_REG 0x090240A4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Error Pin Control.
 * This register provides the option to configure an error pin to either as a 
 * special purpose error pin which is asserted based on the detected error 
 * severity, or as a general purpose output which is asserted based on the value in 
 * the ERRPINDAT. The assertion of the error pins can also be completely disabled 
 * by this register. 
 */
typedef union {
  struct {
    UINT32 pin0 : 2;
    /* pin0 - Bits[1:0], RW, default = 2'b00 
       Error[0] Pin Assertion Control
       11: Reserved.
       10: Assert Error Pin when error severity 0 is set in the system event status 
       reg. 
       01: Assert and Deassert Error pin according to error pin data register.
       00: Disable Error pin assertion
     */
    UINT32 pin1 : 2;
    /* pin1 - Bits[3:2], RW, default = 2'b00 
       Error[1] Pin Assertion Control
       11: Reserved.
       10: Assert Error Pin when error severity 1 is set in the system event status 
       reg. 
       01: Assert and Deassert Error pin according to error pin data register.
       00: Disable Error pin assertion
     */
    UINT32 pin2 : 2;
    /* pin2 - Bits[5:4], RW, default = 2'b00 
       Error[2] Pin Assertion Control11: Reserved.
       10: Assert Error Pin when error severity 2 is set in the system event status 
       reg. 
       01: Assert and Deassert Error pin according to error pin data register.
       00: Disable Error pin assertion
     */
    UINT32 rsvd : 26;
    /* rsvd - Bits[31:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} ERRPINCTL_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* ERRPINSTS_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A0A8)                                                  */
/*       IVT_EX (0x4002A0A8)                                                  */
/*       HSX (0x4002A0A8)                                                     */
/*       BDX (0x4002A0A8)                                                     */
/* Register default value:              0x00000000                            */
#define ERRPINSTS_IIO_RAS_REG 0x090240A8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Error Pin Status.
 * This register reflects the state of the error pin assertion. The status bit of 
 * the corresponding error pin is set upon the deassertion to assertion transition 
 * of the error pin. This bit is cleared by the software with writing 1 to the 
 * corresponding bit. 
 */
typedef union {
  struct {
    UINT32 pin0 : 1;
    /* pin0 - Bits[0:0], RW1CS, default = 1'b0 
       Error[0] Pin status
       This bit is set upon the transition of deassertion to assertion of the Error 
       pin. Software write 1 to clear the status. Hardware will only set this bit when 
       the corresponding ERRPINCTL field is set to 10b. 
     */
    UINT32 pin1 : 1;
    /* pin1 - Bits[1:1], RW1CS, default = 1'b0 
       Error[1] Pin status
       This bit is set upon the transition of deassertion to assertion of the Error 
       pin. Software write 1 to clear the status. Hardware will only set this bit when 
       the corresponding ERRPINCTL field is set to 10b. 
     */
    UINT32 pin2 : 1;
    /* pin2 - Bits[2:2], RW1CS, default = 1'b0 
       Error[2] Pin status
       This bit is set upon the transition of deassertion to assertion of the Error 
       pin. Software write 1 to clear the status. Hardware will only set this bit when 
       the corresponding ERRPINCTL field is set to 10b. 
     */
    UINT32 rsvd : 29;
    /* rsvd - Bits[31:3], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} ERRPINSTS_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* ERRPINDAT_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A0AC)                                                  */
/*       IVT_EX (0x4002A0AC)                                                  */
/*       HSX (0x4002A0AC)                                                     */
/*       BDX (0x4002A0AC)                                                     */
/* Register default value:              0x00000000                            */
#define ERRPINDAT_IIO_RAS_REG 0x090240AC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Error Pin Data.
 * This register provides the data value when the error pin is configured as a 
 * general purpose output. 
 */
typedef union {
  struct {
    UINT32 pin0 : 1;
    /* pin0 - Bits[0:0], RW_LB, default = 1'b0 
       Error[0] Pin Data
       This bit acts as the general purpose output for the Error[0] pin. Software 
       sets/clears this bit to assert/deassert Error[0] pin. This bit applies only when 
       ERRPINCTL[1:0]=01; otherwise it is reserved. 
       
       0: Assert ERR#[0] pin (drive low)
       1: Deassert ERR#[0] pin (float high)
       
       Notes:
       This pin is open drain and must be pulled high by external resistor when 
       deasserted. 
       BIOS needs to write 1 to this bit for security reasons if this register is not 
       used. 
     */
    UINT32 pin1 : 1;
    /* pin1 - Bits[1:1], RW_LB, default = 1'b0 
       Error[1] Pin Data
       This bit acts as the general purpose output for the Error[1] pin. Software 
       sets/clears this bit to assert/deassert Error[1] pin. This bit applies only when 
       ERRPINCTL[3:2]=01; otherwise it is reserved. 
       
       0: Assert ERR#[1] pin (drive low)
       1: Deassert ERR#[1] pin (float high)
       
       Notes:
       This pin is open drain and must be pulled high by external resistor when 
       deasserted. 
       BIOS needs to write 1 to this bit for security reasons if this register is not 
       used. 
     */
    UINT32 pin2 : 1;
    /* pin2 - Bits[2:2], RW_LB, default = 1'b0 
       Error[2] Pin Data
       This bit acts as the general purpose output for the Error[2] pin. Software 
       sets/clears this bit to assert/deassert Error[2] pin. This bit applies only when 
       ERRPINCTL[5:4]=01; otherwise it is reserved. 
       
       0: Assert ERR#[2] pin (drive low)
       1: Deassert ERR#[2] pin (float high)
       
       Notes:
       This pin is open drain and must be pulled high by external resistor when 
       deasserted. 
       BIOS needs to write 1 to this bit for security reasons if this register is not 
       used. 
     */
    UINT32 rsvd : 29;
    /* rsvd - Bits[31:3], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} ERRPINDAT_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* VPPCTL_0_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A0B0)                                                  */
/*       IVT_EX (0x4002A0B0)                                                  */
/*       HSX (0x4002A0B0)                                                     */
/*       BDX (0x4002A0B0)                                                     */
/* Register default value:              0x00000000                            */
#define VPPCTL_0_IIO_RAS_REG 0x090240B0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * VPP Control.
 * This register defines the control/command for PCA9555.
 */
typedef union {
  struct {
    UINT32 vpp_enaddr : 32;
    /* vpp_enaddr - Bits[31:0], RWS, default = 32'b00000000000000000000000000000000 
       Assigns the VPP address of the device on the VPP interface and assigns the port 
       address for the ports within the VPP device. There are more address bits then 
       root ports so assignment must be spread across VPP ports. 
       Addr Port Root Port
       [43:41] [40] Port 3d
       [39:37] [36] Port 3c
       [35:33] [32] Port 3b
       [31:29] [28] Port 3a
       [27:25] [24] Port 2d
       [23:21] [20] Port 2c
       [19:17] [16] Port 2b
       [15:13] [12] Port 2a
       [11:9] [8] Port 1b
       [7:5] [4] Port 1a
       [3:1] [0] Port 0 (PCIe* mode only)
     */
  } Bits;
  UINT32 Data;
} VPPCTL_0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* VPPCTL_1_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A0B4)                                                  */
/*       IVT_EX (0x4002A0B4)                                                  */
/*       HSX (0x4002A0B4)                                                     */
/*       BDX (0x4002A0B4)                                                     */
/* Register default value:              0x10000000                            */
#define VPPCTL_1_IIO_RAS_REG 0x090240B4


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x0b4
 */
typedef union {
  struct {
    UINT32 vpp_enaddr2 : 12;
    /* vpp_enaddr2 - Bits[11:0], RWS, default = 12'b000000000000 
       Upper bits of vppctl_1.vpp_enaddr.
     */
    UINT32 vpp_en : 11;
    /* vpp_en - Bits[22:12], RWS, default = 11'b00000000000 
       When set, the VPP function for the corresponding root port is enabled.
       Enable Root Port
       [54] Port 3d
       [53] Port 3c
       [52] Port 3b
       [51] Port 3a
       [50] Port 2d
       [49] Port 2c
       [48] Port 2b
       [47] Port 2a
       [46] Unused
       [45] Unused
       [44] Port 0 (PCIe* mode only)
     */
    UINT32 vpp_reset_mode : 1;
    /* vpp_reset_mode - Bits[23:23], RWS, default = 1'b0 
       0: Power good reset will reset the VPP state machines and hard reset will cause 
       the VPP state machine to terminate at the next 'logical' VPP stream boundary and 
       then reset the VPP state machines 
       1: Both power good and hard reset will reset the VPP state machines
     */
    UINT32 vpp_stop_smbus_inj : 3;
    /* vpp_stop_smbus_inj - Bits[26:24], RWS, default = 3'b000  */
    UINT32 rsvd : 1;
    /* rsvd - Bits[27:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 vpp_version : 4;
    /* vpp_version - Bits[31:28], RO, default = 4'b0001 
       Specified the version of this structure for BIOS use.
       0: VPPCTL with 11 PCIe ports.
       1: VPPCTL with 11 PCIe prots + VPPMEM with 4 memory ports.
     */
  } Bits;
  UINT32 Data;
} VPPCTL_1_IIO_RAS_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* VPPSTS_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x4002A0B8)                                                  */
/*       IVT_EX (0x4002A0B8)                                                  */
/*       HSX (0x4002A0B8)                                                     */
/*       BDX (0x4002A0B8)                                                     */
/* Register default value:              0x00000000                            */
#define VPPSTS_IIO_RAS_REG 0x090240B8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * VPP Status.
 * This register defines the status from PCA9555.
 */
typedef union {
  struct {
    UINT32 vpp_error : 1;
    /* vpp_error - Bits[0:0], RW1CS, default = 1'b0 
       VPP Port error happened i.e. an unexpected STOP of NACK was seen on the VPP port
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VPPSTS_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* VPPFREQ_IIO_RAS_REG supported on:                                          */
/*       IVT_EP (0x4002A0BC)                                                  */
/*       IVT_EX (0x4002A0BC)                                                  */
/*       HSX (0x4002A0BC)                                                     */
/*       BDX (0x4002A0BC)                                                     */
/* Register default value:              0x1E9609C4                            */
#define VPPFREQ_IIO_RAS_REG 0x090240BC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * VPP Frequency Control.
 * 
 */
typedef union {
  struct {
    UINT32 vpp_tsu_thd : 12;
    /* vpp_tsu_thd - Bits[11:0], RWS, default = 12'b100111000100 
       VPP Tsu and Thd
       Represents the high time and low time of the SCL pin. It should be set to 5uS 
       for a 100kHz SCL clock (5uS high time and 5uS low time). The default value 
       represents 5uS with an internal clock of 500MHz. 
     */
    UINT32 rsvd : 4;
    /* rsvd - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 vpp_thd_data : 8;
    /* vpp_thd_data - Bits[23:16], RWS, default = 8'b10010110 
       VPP Thd Data (Hold Time on Data)
       Hold time for Data is 300nS. The default value is set to 300nS when the internal 
       clock rate is 500MHz. 
     */
    UINT32 vpp_tpf : 8;
    /* vpp_tpf - Bits[31:24], RWS, default = 8'b00011110 
       VPP Tpf (Pulse Filter Time)
       Pulse Filter should be set to 60nS. The value used is dependent on the internal 
       clock frequency. In this case, internal clock frequency is 500MHz, so the 
       default value represents 60nS at that rate. 
     */
  } Bits;
  UINT32 Data;
} VPPFREQ_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* VPPMEM_N0_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A0C0)                                                  */
/*       IVT_EX (0x4002A0C0)                                                  */
/*       HSX (0x4002A0C0)                                                     */
/*       BDX (0x4002A0C0)                                                     */
/* Register default value:              0x00000000                            */
#define VPPMEM_N0_IIO_RAS_REG 0x090240C0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 */
typedef union {
  struct {
    UINT32 vpp_enaddr2 : 32;
    /* vpp_enaddr2 - Bits[31:0], RWS, default = 32'b00000000000000000000000000000000 
       Assigns the VPP address of the device on the VPP interface and assigns the port 
       address for the ports within the VPP device. There are for memory channel 
       hotplug. 
       Port Addr Root Port
       [31] [30:28] Reserved
       [27] [27:24] Reserved
       [23] [22:20] Reserved
       [19] [18:16] Reserved
       [15] [14:12] Memory Channel 3
       [11] [10:8] Memory Channel 2
       [7] [6:4] Memory Channel 1
       [3] [2:0] Memory Channel 0
     */
  } Bits;
  UINT32 Data;
} VPPMEM_N0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* VPPMEM_N1_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A0C4)                                                  */
/*       IVT_EX (0x4002A0C4)                                                  */
/*       HSX (0x4002A0C4)                                                     */
/*       BDX (0x4002A0C4)                                                     */
/* Register default value:              0x00000000                            */
#define VPPMEM_N1_IIO_RAS_REG 0x090240C4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 */
typedef union {
  struct {
    UINT32 vpp_en : 8;
    /* vpp_en - Bits[7:0], RWS, default = 8'b00000000 
       When set, the VPP function for the corresponding root port is enabled.
       Enable Root Port
       [39] reserved.
       [38] reserved.
       [37] reserved.
       [36] reserved.
       [35] Memory Channel 3
       [34] Memory Channel 2
       [33] Memory Channel 1
       [32] Memory Channel 0
     */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VPPMEM_N1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* VPP_INVERTS_IIO_RAS_REG supported on:                                      */
/*       IVT_EP (0x4002A0C8)                                                  */
/*       IVT_EX (0x4002A0C8)                                                  */
/*       HSX (0x4002A0C8)                                                     */
/*       BDX (0x4002A0C8)                                                     */
/* Register default value:              0x00000000                            */
#define VPP_INVERTS_IIO_RAS_REG 0x090240C8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x0c8
 */
typedef union {
  struct {
    UINT32 dfr_inv_pwren : 1;
    /* dfr_inv_pwren - Bits[0:0], RWS, default = 1'b0 
       Inverts the PWREN signal
     */
    UINT32 dfr_inv_emil : 1;
    /* dfr_inv_emil - Bits[1:1], RWS, default = 1'b0 
       Inverts the EMIL signal
     */
    UINT32 dfr_inv_mrl : 1;
    /* dfr_inv_mrl - Bits[2:2], RWS, default = 1'b0 
       Inverts the MRL signal
     */
    UINT32 rsvd : 29;
    /* rsvd - Bits[31:3], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VPP_INVERTS_IIO_RAS_STRUCT;
#endif /* ASM_INC */




/* GNERRMASK_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A19C)                                                  */
/*       IVT_EX (0x4002A19C)                                                  */
/*       HSX (0x4002A19C)                                                     */
/*       BDX (0x4002A19C)                                                     */
/* Register default value:              0x00000000                            */
#define GNERRMASK_IIO_RAS_REG 0x0902419C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Non-Fatal Error Mask.
 * This register masks the reporting of errors detected by the IIO local 
 * interfaces. An individual error control bit that is set masks error signaling of 
 * the particular local interface; software may set or clear the mask bit. Note 
 * that bit fields in this register can become reserved depending on the port 
 * configuration. For example, if the PCI-E port is configured as 2X8 ports, then 
 * only the corresponding PCI-E X8 bit fields are valid.  
 */
typedef union {
  struct {
    UINT32 csi_err_msk0 : 1;
    /* csi_err_msk0 - Bits[0:0], RW, default = 1'b0 
       IRP1 Coherent Interface Error
     */
    UINT32 csi_err_msk1 : 1;
    /* csi_err_msk1 - Bits[1:1], RW, default = 1'b0 
       IRP0 Coherent Interface Error
     */
    UINT32 rsvd_2 : 3;
    UINT32 pcie_err_msk0 : 1;
    /* pcie_err_msk0 - Bits[5:5], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 0
     */
    UINT32 pcie_err_msk1 : 1;
    /* pcie_err_msk1 - Bits[6:6], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 1a
     */
    UINT32 pcie_err_msk2 : 1;
    /* pcie_err_msk2 - Bits[7:7], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 1b
     */
    UINT32 pcie_err_msk3 : 1;
    /* pcie_err_msk3 - Bits[8:8], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 2a
     */
    UINT32 pcie_err_msk4 : 1;
    /* pcie_err_msk4 - Bits[9:9], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 2b
     */
    UINT32 pcie_err_msk5 : 1;
    /* pcie_err_msk5 - Bits[10:10], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 2c
     */
    UINT32 pcie_err_msk6 : 1;
    /* pcie_err_msk6 - Bits[11:11], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 2d
     */
    UINT32 pcie_err_msk7 : 1;
    /* pcie_err_msk7 - Bits[12:12], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 3a
     */
    UINT32 pcie_err_msk8 : 1;
    /* pcie_err_msk8 - Bits[13:13], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 3b
     */
    UINT32 pcie_err_msk9 : 1;
    /* pcie_err_msk9 - Bits[14:14], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 3c
     */
    UINT32 pcie_err_msk10 : 1;
    /* pcie_err_msk10 - Bits[15:15], RW, default = 1'b0 
       PCIe* Error Mask: Mask bit for associated PCIe* logical Port 3d
     */
    UINT32 rsvd_16 : 4;
    /* rsvd_16 - Bits[19:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dmi_err_msk : 1;
    /* dmi_err_msk - Bits[20:20], RW, default = 1'b0 
       DMI Error Mask
     */
    UINT32 rsvd_21 : 2;
    UINT32 ioh_err_msk : 1;
    /* ioh_err_msk - Bits[23:23], RW, default = 1'b0 
       IIO Core Error Mask
     */
    UINT32 mi_err_msk : 1;
    /* mi_err_msk - Bits[24:24], RW, default = 1'b0 
       Miscellaneous Error Mask
     */
    UINT32 vtd_err_msk : 1;
    /* vtd_err_msk - Bits[25:25], RW, default = 1'b0 
       Intel VT-d Error Mask
     */
    UINT32 rsvd_26 : 6;
    /* rsvd_26 - Bits[31:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GNERRMASK_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GFERRMASK_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A1A0)                                                  */
/*       IVT_EX (0x4002A1A0)                                                  */
/*       HSX (0x4002A1A0)                                                     */
/*       BDX (0x4002A1A0)                                                     */
/* Register default value:              0x00000000                            */
#define GFERRMASK_IIO_RAS_REG 0x090241A0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Fatal Error Mask.
 * This register masks the reporting of errors detected by the IIO local 
 * interfaces. An individual error control bit that is set masks error signaling of 
 * the particular local interface; software may set or clear the mask bit. Note 
 * that bit fields in this register can become reserved depending on the port 
 * configuration. For example, if the PCI-E port is configured as 2X8 ports, then 
 * only the corresponding PCI-E X8 bit fields are valid.  
 */
typedef union {
  struct {
    UINT32 csi_err_msk0 : 1;
    /* csi_err_msk0 - Bits[0:0], RW, default = 1'b0 
       IRP0 Coherent Interface Error Mask
     */
    UINT32 csi_err_msk1 : 1;
    /* csi_err_msk1 - Bits[1:1], RW, default = 1'b0 
       IRP1 Coherent Interface Error Mask
     */
    UINT32 rsvd_2 : 3;
    UINT32 pcie_err_msk0 : 1;
    /* pcie_err_msk0 - Bits[5:5], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 0
     */
    UINT32 pcie_err_msk1 : 1;
    /* pcie_err_msk1 - Bits[6:6], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 1a
     */
    UINT32 pcie_err_msk2 : 1;
    /* pcie_err_msk2 - Bits[7:7], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 1b
     */
    UINT32 pcie_err_msk3 : 1;
    /* pcie_err_msk3 - Bits[8:8], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2a
     */
    UINT32 pcie_err_msk4 : 1;
    /* pcie_err_msk4 - Bits[9:9], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2b
     */
    UINT32 pcie_err_msk5 : 1;
    /* pcie_err_msk5 - Bits[10:10], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2c
     */
    UINT32 pcie_err_msk6 : 1;
    /* pcie_err_msk6 - Bits[11:11], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2d
     */
    UINT32 pcie_err_msk7 : 1;
    /* pcie_err_msk7 - Bits[12:12], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 3a
     */
    UINT32 pcie_err_msk8 : 1;
    /* pcie_err_msk8 - Bits[13:13], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 3b
     */
    UINT32 pcie_err_msk9 : 1;
    /* pcie_err_msk9 - Bits[14:14], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 3c
     */
    UINT32 pcie_err_msk10 : 1;
    /* pcie_err_msk10 - Bits[15:15], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 3d
     */
    UINT32 rsvd_16 : 4;
    /* rsvd_16 - Bits[19:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dmi_err_msk : 1;
    /* dmi_err_msk - Bits[20:20], RW, default = 1'b0 
       DMI Error Mask
     */
    UINT32 rsvd_21 : 2;
    UINT32 ioh_err_msk : 1;
    /* ioh_err_msk - Bits[23:23], RW, default = 1'b0  */
    UINT32 mi_err_msk : 1;
    /* mi_err_msk - Bits[24:24], RW, default = 1'b0 
       Miscellaneous Error Mask
     */
    UINT32 vtd_err_msk : 1;
    /* vtd_err_msk - Bits[25:25], RW, default = 1'b0 
       Intel VT-d Error Mask
     */
    UINT32 rsvd_26 : 6;
    /* rsvd_26 - Bits[31:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GFERRMASK_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GCERRMASK_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A1A4)                                                  */
/*       IVT_EX (0x4002A1A4)                                                  */
/*       HSX (0x4002A1A4)                                                     */
/*       BDX (0x4002A1A4)                                                     */
/* Register default value:              0x00000000                            */
#define GCERRMASK_IIO_RAS_REG 0x090241A4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Corrected Error Mask.
 * This register masks the reporting of errors detected by the IIO local 
 * interfaces. An individual error control bit that is set masks error signaling of 
 * the particular local interface; software may set or clear the mask bit. Note 
 * that bit fields in this register can become reserved depending on the port 
 * configuration. For example, if the PCI-E port is configured as 2X8 ports, then 
 * only the corresponding PCI-E X8 bit fields are valid;  
 */
typedef union {
  struct {
    UINT32 csi_err_msk0 : 1;
    /* csi_err_msk0 - Bits[0:0], RW, default = 1'b0 
       IRP0 Coherent Interface Error Mask
     */
    UINT32 csi_err_msk1 : 1;
    /* csi_err_msk1 - Bits[1:1], RW, default = 1'b0 
       IRP1 Coherent Interface Error Mask
     */
    UINT32 rsvd_2 : 3;
    UINT32 pcie_err_msk0 : 1;
    /* pcie_err_msk0 - Bits[5:5], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 0
     */
    UINT32 pcie_err_msk1 : 1;
    /* pcie_err_msk1 - Bits[6:6], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 1a
     */
    UINT32 pcie_err_msk2 : 1;
    /* pcie_err_msk2 - Bits[7:7], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2b
     */
    UINT32 pcie_err_msk3 : 1;
    /* pcie_err_msk3 - Bits[8:8], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2a
     */
    UINT32 pcie_err_msk4 : 1;
    /* pcie_err_msk4 - Bits[9:9], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2b
     */
    UINT32 pcie_err_msk5 : 1;
    /* pcie_err_msk5 - Bits[10:10], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2c
     */
    UINT32 pcie_err_msk6 : 1;
    /* pcie_err_msk6 - Bits[11:11], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 2d
     */
    UINT32 pcie_err_msk7 : 1;
    /* pcie_err_msk7 - Bits[12:12], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 3a
     */
    UINT32 pcie_err_msk8 : 1;
    /* pcie_err_msk8 - Bits[13:13], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 3b
     */
    UINT32 pcie_err_msk9 : 1;
    /* pcie_err_msk9 - Bits[14:14], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 3c
     */
    UINT32 pcie_err_msk10 : 1;
    /* pcie_err_msk10 - Bits[15:15], RW, default = 1'b0 
       Mask bit for associated PCIe* logical Port 3d
     */
    UINT32 rsvd_16 : 4;
    /* rsvd_16 - Bits[19:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dmi_err_msk : 1;
    /* dmi_err_msk - Bits[20:20], RW, default = 1'b0 
       DMI Error Mask
     */
    UINT32 therm_err_msk : 1;
    /* therm_err_msk - Bits[21:21], RW, default = 1'b0  */
    UINT32 rsvd_22 : 1;
    UINT32 ioh_err_msk : 1;
    /* ioh_err_msk - Bits[23:23], RW, default = 1'b0 
       IIO Core Error Mask
     */
    UINT32 mi_err_msk : 1;
    /* mi_err_msk - Bits[24:24], RW, default = 1'b0 
       Miscellaneous Error Mask
     */
    UINT32 vtd_err_msk : 1;
    /* vtd_err_msk - Bits[25:25], RW, default = 1'b0 
       Intel VT-d Error Mask
     */
    UINT32 mc_err_msk : 1;
    /* mc_err_msk - Bits[26:26], RW, default = 1'b0 
       Memory Controller Error Mask.
     */
    UINT32 rsvd_27 : 5;
    /* rsvd_27 - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GCERRMASK_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GCERRST_IIO_RAS_REG supported on:                                          */
/*       IVT_EP (0x4002A1A8)                                                  */
/*       IVT_EX (0x4002A1A8)                                                  */
/*       HSX (0x4002A1A8)                                                     */
/*       BDX (0x4002A1A8)                                                     */
/* Register default value:              0x00000000                            */
#define GCERRST_IIO_RAS_REG 0x090241A8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Corrected Error Status.
 * This register indicates the corrected error reported to the IIO global error 
 * logic. An individual error status bit that is set indicates that a particular 
 * local interface has detected an error. 
 */
typedef union {
  struct {
    UINT32 csi0_err : 1;
    /* csi0_err - Bits[0:0], RW1CS, default = 1'b0 
       IRP0 Coherent Interface Error
     */
    UINT32 csi1_err : 1;
    /* csi1_err - Bits[1:1], RW1CS, default = 1'b0 
       IRP1 Coherent Interface Error
     */
    UINT32 rsvd_2 : 3;
    UINT32 pcie0 : 1;
    /* pcie0 - Bits[5:5], RW1CS, default = 1'b0 
       Bit 5: Port 0 PCIe* logical port has detected an error.
     */
    UINT32 pcie1 : 1;
    /* pcie1 - Bits[6:6], RW1CS, default = 1'b0 
       Port 1a PCIe* logical port has detected an error.
     */
    UINT32 pcie2 : 1;
    /* pcie2 - Bits[7:7], RW1CS, default = 1'b0 
       Port 1b PCIe* logical port has detected an error.
     */
    UINT32 pcie3 : 1;
    /* pcie3 - Bits[8:8], RW1CS, default = 1'b0 
       Port 2a PCIe* logical port has detected an error.
     */
    UINT32 pcie4 : 1;
    /* pcie4 - Bits[9:9], RW1CS, default = 1'b0 
       Port 2b PCIe* logical port has detected an error.
     */
    UINT32 pcie5 : 1;
    /* pcie5 - Bits[10:10], RW1CS, default = 1'b0 
       Port 2c PCIe* logical port has detected an error.
     */
    UINT32 pcie6 : 1;
    /* pcie6 - Bits[11:11], RW1CS, default = 1'b0 
       Port 2d PCIe* logical port has detected an error.
     */
    UINT32 pcie7 : 1;
    /* pcie7 - Bits[12:12], RW1CS, default = 1'b0 
       Port 3a PCIe* logical port has detected an error.
     */
    UINT32 pcie8 : 1;
    /* pcie8 - Bits[13:13], RW1CS, default = 1'b0 
       Port 3b PCIe* logical port has detected an error.
     */
    UINT32 pcie9 : 1;
    /* pcie9 - Bits[14:14], RW1CS, default = 1'b0 
       Port 3c PCIe* logical port has detected an error.
     */
    UINT32 pcie10 : 1;
    /* pcie10 - Bits[15:15], RW1CS, default = 1'b0 
       Port 3d PCIe* logical port has detected an error.
     */
    UINT32 rsvd_16 : 4;
    /* rsvd_16 - Bits[19:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dmi : 1;
    /* dmi - Bits[20:20], RW1CS, default = 1'b0 
       DMI Error Status
       This bit indicates that IIO DMI port 0 has detected an error.
     */
    UINT32 rsvd_21 : 2;
    UINT32 ioh : 1;
    /* ioh - Bits[23:23], RW1CS, default = 1'b0 
       IIO Core Error Status
       This bit indicates that IIO core has detected an error.
     */
    UINT32 mi : 1;
    /* mi - Bits[24:24], RW1CS, default = 1'b0 
       Miscellaneous Error Status
     */
    UINT32 vtd : 1;
    /* vtd - Bits[25:25], RW1CS, default = 1'b0 
       Intel VT-d Error Status
       This register indicates the corrected error reported to the Intel VT-d error 
       logic. An individual error status bit that is set indicates that a particular 
       local interface has detected an error. 
     */
    UINT32 mc : 1;
    /* mc - Bits[26:26], RW1CS, default = 1'b0 
       Memory Controller Error Status.
     */
    UINT32 rsvd_27 : 5;
    /* rsvd_27 - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GCERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GCFERRST_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A1AC)                                                  */
/*       IVT_EX (0x4002A1AC)                                                  */
/*       HSX (0x4002A1AC)                                                     */
/*       BDX (0x4002A1AC)                                                     */
/* Register default value:              0x00000000                            */
#define GCFERRST_IIO_RAS_REG 0x090241AC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Corrected FERR Status.
 */
typedef union {
  struct {
    UINT32 log : 27;
    /* log - Bits[26:0], ROS_V, default = 27'b000000000000000000000000000 
       This field logs the global error status register content when the first 
       corrected error is reported. This has the same format as the global corrected 
       error status register (GCERRST). 
     */
    UINT32 rsvd : 5;
    /* rsvd - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GCFERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */






/* GCNERRST_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A1B8)                                                  */
/*       IVT_EX (0x4002A1B8)                                                  */
/*       HSX (0x4002A1B8)                                                     */
/*       BDX (0x4002A1B8)                                                     */
/* Register default value:              0x00000000                            */
#define GCNERRST_IIO_RAS_REG 0x090241B8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Corrected NERR Status.
 */
typedef union {
  struct {
    UINT32 log : 27;
    /* log - Bits[26:0], ROS_V, default = 27'b000000000000000000000000000 
       This field logs the global error status register content when the first 
       corrected error is reported. This has the same format as the global corrected 
       error status register (GCERRST). 
     */
    UINT32 rsvd : 5;
    /* rsvd - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GCNERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GNERRST_IIO_RAS_REG supported on:                                          */
/*       IVT_EP (0x4002A1C0)                                                  */
/*       IVT_EX (0x4002A1C0)                                                  */
/*       HSX (0x4002A1C0)                                                     */
/*       BDX (0x4002A1C0)                                                     */
/* Register default value:              0x00000000                            */
#define GNERRST_IIO_RAS_REG 0x090241C0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Nonfatal Error Status.
 * This register indicates the non-fatal error reported to the IIO global error 
 * logic. An individual error status bit that is set indicates that a particular 
 * local interface has detected an error. 
 */
typedef union {
  struct {
    UINT32 csi0_err : 1;
    /* csi0_err - Bits[0:0], RW1CS, default = 1'b0 
       IRP0 Coherent Interface Error
     */
    UINT32 csi1_err : 1;
    /* csi1_err - Bits[1:1], RW1CS, default = 1'b0 
       IRP1 Coherent Interface Error
     */
    UINT32 rsvd_2 : 3;
    UINT32 pcie0 : 1;
    /* pcie0 - Bits[5:5], RW1CS, default = 1'b0 
       Port 0 PCIe* logical port has detected an error.
     */
    UINT32 pcie1 : 1;
    /* pcie1 - Bits[6:6], RW1CS, default = 1'b0 
       Port 1a PCIe* logical port has detected an error.
     */
    UINT32 pcie2 : 1;
    /* pcie2 - Bits[7:7], RW1CS, default = 1'b0 
       Port 1b PCIe* logical port has detected an error.
     */
    UINT32 pcie3 : 1;
    /* pcie3 - Bits[8:8], RW1CS, default = 1'b0 
       Port 2a PCIe* logical port has detected an error.
     */
    UINT32 pcie4 : 1;
    /* pcie4 - Bits[9:9], RW1CS, default = 1'b0 
       Port 2b PCIe* logical port has detected an error.
     */
    UINT32 pcie5 : 1;
    /* pcie5 - Bits[10:10], RW1CS, default = 1'b0 
       Port 2c PCIe* logical port has detected an error.
     */
    UINT32 pcie6 : 1;
    /* pcie6 - Bits[11:11], RW1CS, default = 1'b0 
       Port 2d PCIe* logical port has detected an error.
     */
    UINT32 pcie7 : 1;
    /* pcie7 - Bits[12:12], RW1CS, default = 1'b0 
       Port 3a PCIe* logical port has detected an error.
     */
    UINT32 pcie8 : 1;
    /* pcie8 - Bits[13:13], RW1CS, default = 1'b0 
       Port 3b PCIe* logical port has detected an error.
     */
    UINT32 pcie9 : 1;
    /* pcie9 - Bits[14:14], RW1CS, default = 1'b0 
       Port 3c PCIe* logical port has detected an error.
     */
    UINT32 pcie10 : 1;
    /* pcie10 - Bits[15:15], RW1CS, default = 1'b0 
       Port 3d PCIe* logical port has detected an error.
     */
    UINT32 rsvd_16 : 4;
    /* rsvd_16 - Bits[19:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dmi : 1;
    /* dmi - Bits[20:20], RW1CS, default = 1'b0 
       DMI Error Status
       This bit indicates that IIO DMI port 0 has detected an error.
     */
    UINT32 rsvd_21 : 2;
    UINT32 ioh : 1;
    /* ioh - Bits[23:23], RW1CS, default = 1'b0 
       IIO Core Error Status
       This bit indicates that IIO core has detected an error
     */
    UINT32 mi : 1;
    /* mi - Bits[24:24], RW1CS, default = 1'b0 
       Miscellaneous Error Status
     */
    UINT32 vtd : 1;
    /* vtd - Bits[25:25], RW1CS, default = 1'b0 
       Intel VT-d Error Status
       This register indicates the non-fatal error reported to the Intel VT-d error 
       logic. An individual error status bit that is set indicates that a particular 
       local interface has detected an error. 
     */
    UINT32 rsvd_26 : 6;
    /* rsvd_26 - Bits[31:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GNERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GFERRST_IIO_RAS_REG supported on:                                          */
/*       IVT_EP (0x4002A1C4)                                                  */
/*       IVT_EX (0x4002A1C4)                                                  */
/*       HSX (0x4002A1C4)                                                     */
/*       BDX (0x4002A1C4)                                                     */
/* Register default value:              0x00000000                            */
#define GFERRST_IIO_RAS_REG 0x090241C4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Fatal Error Status.
 * This register indicates the fatal error reported to the IIO global error logic. 
 * An individual error status bit that is set indicates that a particular local 
 * interface has detected an error. 
 */
typedef union {
  struct {
    UINT32 tras_csi0 : 1;
    /* tras_csi0 - Bits[0:0], RW1CS, default = 1'b0 
       IRP0 Coherent Interface Error
     */
    UINT32 tras_csi1 : 1;
    /* tras_csi1 - Bits[1:1], RW1CS, default = 1'b0 
       IRP1 Coherent Interface Error
     */
    UINT32 rsvd_2 : 3;
    UINT32 pcie0 : 1;
    /* pcie0 - Bits[5:5], RW1CS, default = 1'b0 
       Port 0 PCIe* logical port has detected an error.
     */
    UINT32 pcie1 : 1;
    /* pcie1 - Bits[6:6], RW1CS, default = 1'b0 
       Port 1a PCIe* logical port has detected an error.
     */
    UINT32 pcie2 : 1;
    /* pcie2 - Bits[7:7], RW1CS, default = 1'b0 
       Port 1b PCIe* logical port has detected an error.
     */
    UINT32 pcie3 : 1;
    /* pcie3 - Bits[8:8], RW1CS, default = 1'b0 
       Port 2a PCIe* logical port has detected an error.
     */
    UINT32 pcie4 : 1;
    /* pcie4 - Bits[9:9], RW1CS, default = 1'b0 
       Port 2b PCIe* logical port has detected an error.
     */
    UINT32 pcie5 : 1;
    /* pcie5 - Bits[10:10], RW1CS, default = 1'b0 
       Port 2c PCIe* logical port has detected an error.
     */
    UINT32 pcie6 : 1;
    /* pcie6 - Bits[11:11], RW1CS, default = 1'b0 
       Port 2d PCIe* logical port has detected an error.
     */
    UINT32 pcie7 : 1;
    /* pcie7 - Bits[12:12], RW1CS, default = 1'b0 
       Port 3a PCIe* logical port has detected an error.
     */
    UINT32 pcie8 : 1;
    /* pcie8 - Bits[13:13], RW1CS, default = 1'b0 
       Port 3b PCIe* logical port has detected an error.
     */
    UINT32 pcie9 : 1;
    /* pcie9 - Bits[14:14], RW1CS, default = 1'b0 
       Port 3c PCIe* logical port has detected an error.
     */
    UINT32 pcie10 : 1;
    /* pcie10 - Bits[15:15], RW1CS, default = 1'b0 
       Port 3d PCIe* logical port has detected an error.
     */
    UINT32 rsvd_16 : 4;
    /* rsvd_16 - Bits[19:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dmi : 1;
    /* dmi - Bits[20:20], RW1CS, default = 1'b0 
       DMI Error Status
       This bit indicates that IIO DMI port 0 has detected an error.
     */
    UINT32 rsvd_21 : 2;
    UINT32 ioh : 1;
    /* ioh - Bits[23:23], RW1CS, default = 1'b0 
       IIO Core Error Status
       This bit indicates that IIO core has detected an error
     */
    UINT32 mi : 1;
    /* mi - Bits[24:24], RW1CS, default = 1'b0 
       Miscellaneous Error Status
     */
    UINT32 vtd : 1;
    /* vtd - Bits[25:25], RW1CS, default = 1'b0 
       Intel VT-d Error Status
       This register indicates the fatal error reported to the Intel VT-d error logic. 
       An individual error status bit that is set indicates that a particular local 
       interface has detected an error. 
     */
    UINT32 rsvd_26 : 6;
    /* rsvd_26 - Bits[31:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GFERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GERRCTL_IIO_RAS_REG supported on:                                          */
/*       IVT_EP (0x4002A1C8)                                                  */
/*       IVT_EX (0x4002A1C8)                                                  */
/*       HSX (0x4002A1C8)                                                     */
/*       BDX (0x4002A1C8)                                                     */
/* Register default value:              0x00000000                            */
#define GERRCTL_IIO_RAS_REG 0x090241C8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Error Control.
 * This register controls/masks the reporting of errors detected by the IIO local 
 * interfaces. An individual error control bit that is set masks error reporting of 
 * the particular local interface; software may set or clear the control bit. This 
 * register is sticky and can only be reset by PWRGOOD. Note that bit fields in 
 * this register can become reserved depending on the port configuration. For 
 * example, if the PCI-E port is configured as 2X8 ports, then only the 
 * corresponding PCI-EX8 bit fields are valid; other bits are unused and 
 * reserved.Global error control register masks errors reported from the local 
 * interface to the global register. If the an error reporting is disabled in this 
 * register, all errors from the corresponding local interface will not set any of 
 * the global error status bits. 
 */
typedef union {
  struct {
    UINT32 csi_err_msk0 : 1;
    /* csi_err_msk0 - Bits[0:0], RW, default = 1'b0 
       IRP0 Error Mask
     */
    UINT32 csi_err_msk1 : 1;
    /* csi_err_msk1 - Bits[1:1], RW, default = 1'b0 
       IRP1 Error Mask
     */
    UINT32 csip_err_msk0 : 1;
    /* csip_err_msk0 - Bits[2:2], RW, default = 1'b0 
       1
     */
    UINT32 csip_err_msk1 : 1;
    /* csip_err_msk1 - Bits[3:3], RW, default = 1'b0 
       1
     */
    UINT32 rsvd_4 : 1;
    /* rsvd_4 - Bits[4:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pcie_err_msk0 : 1;
    /* pcie_err_msk0 - Bits[5:5], RW, default = 1'b0 
       Port 0 PCIe error mask.
     */
    UINT32 pcie_err_msk1 : 1;
    /* pcie_err_msk1 - Bits[6:6], RW, default = 1'b0 
       Port 1a PCIe error mask.
     */
    UINT32 pcie_err_msk2 : 1;
    /* pcie_err_msk2 - Bits[7:7], RW, default = 1'b0 
       Port 1b PCIe error mask.
     */
    UINT32 pcie_err_msk3 : 1;
    /* pcie_err_msk3 - Bits[8:8], RW, default = 1'b0 
       Port 2a PCIe error mask.
     */
    UINT32 pcie_err_msk4 : 1;
    /* pcie_err_msk4 - Bits[9:9], RW, default = 1'b0 
       Port 2b PCIe error mask.
     */
    UINT32 pcie_err_msk5 : 1;
    /* pcie_err_msk5 - Bits[10:10], RW, default = 1'b0 
       Port 2c PCIe error mask.
     */
    UINT32 pcie_err_msk6 : 1;
    /* pcie_err_msk6 - Bits[11:11], RW, default = 1'b0 
       Port 2d PCIe error mask.
     */
    UINT32 pcie_err_msk7 : 1;
    /* pcie_err_msk7 - Bits[12:12], RW, default = 1'b0 
       Port 3a PCIe error mask.
     */
    UINT32 pcie_err_msk8 : 1;
    /* pcie_err_msk8 - Bits[13:13], RW, default = 1'b0 
       Port 3b PCIe error mask.
     */
    UINT32 pcie_err_msk9 : 1;
    /* pcie_err_msk9 - Bits[14:14], RW, default = 1'b0 
       Port 3c PCIe error mask.
     */
    UINT32 pcie_err_msk10 : 1;
    /* pcie_err_msk10 - Bits[15:15], RW, default = 1'b0 
       Port 3d PCIe error mask.
     */
    UINT32 rsvd_16 : 4;
    /* rsvd_16 - Bits[19:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dmi_err_msk : 1;
    /* dmi_err_msk - Bits[20:20], RW, default = 1'b0 
       DMI Error Enable
       This bit enables/masks the error detected in the DMI[0] Port.
     */
    UINT32 therm_err_msk : 1;
    /* therm_err_msk - Bits[21:21], RW, default = 1'b0 
       1
     */
    UINT32 dma_err_msk : 1;
    /* dma_err_msk - Bits[22:22], RW, default = 1'b0 
       DMA Engine Error Mask
     */
    UINT32 ioh_err_msk : 1;
    /* ioh_err_msk - Bits[23:23], RW, default = 1'b0 
       IIO Core Error Enable
       This bit enables/masks the error detected in the IIO Core.
     */
    UINT32 mi_err_msk : 1;
    /* mi_err_msk - Bits[24:24], RW, default = 1'b0 
       Miscellaneous Error Mask
     */
    UINT32 vtd_err_msk : 1;
    /* vtd_err_msk - Bits[25:25], RW, default = 1'b0 
       Intel VT-d Error Mask
     */
    UINT32 mc_err_msk : 1;
    /* mc_err_msk - Bits[26:26], RW, default = 1'b0 
       Memory Controller Error Mask.
     */
    UINT32 rsvd_27 : 5;
    /* rsvd_27 - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GERRCTL_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GSYSST_IIO_RAS_REG supported on:                                           */
/*       IVT_EP (0x4002A1CC)                                                  */
/*       IVT_EX (0x4002A1CC)                                                  */
/*       HSX (0x4002A1CC)                                                     */
/*       BDX (0x4002A1CC)                                                     */
/* Register default value:              0x00000000                            */
#define GSYSST_IIO_RAS_REG 0x090241CC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global System Event Status.
 * This register indicates the error severity signaled by the IIO global error 
 * logic. Setting of an individual error status bit indicates that the 
 * corresponding error severity has been detected by the IIO. 
 */
typedef union {
  struct {
    UINT32 sev0 : 1;
    /* sev0 - Bits[0:0], ROS_V, default = 1'b0 
       When set, IIO has detected an error of error severity 0
     */
    UINT32 sev1 : 1;
    /* sev1 - Bits[1:1], ROS_V, default = 1'b0 
       When set, IIO has detected an error of error severity 1
     */
    UINT32 sev2 : 1;
    /* sev2 - Bits[2:2], ROS_V, default = 1'b0 
       When set, IIO has detected an error of error severity 2
     */
    UINT32 rsvd_3 : 29;
  } Bits;
  UINT32 Data;
} GSYSST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GSYSCTL_IIO_RAS_REG supported on:                                          */
/*       IVT_EP (0x4002A1D0)                                                  */
/*       IVT_EX (0x4002A1D0)                                                  */
/*       HSX (0x4002A1D0)                                                     */
/*       BDX (0x4002A1D0)                                                     */
/* Register default value:              0x00000000                            */
#define GSYSCTL_IIO_RAS_REG 0x090241D0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global System Event Control.
 * The system event control register controls/masks the reporting the errors 
 * indicated by the system event status register. When cleared, the error severity 
 * does not cause the generation of the system event. When set, detection of the 
 * error severity generates system event(s) according to system event map register 
 * (SYSMAP). 
 */
typedef union {
  struct {
    UINT32 sev0_en : 1;
    /* sev0_en - Bits[0:0], RW, default = 1'b0 
       When set, the detection of error severity 0 generates system events.
     */
    UINT32 sev1_en : 1;
    /* sev1_en - Bits[1:1], RW, default = 1'b0 
       When set, the detection of error severity 1 generates system events.
     */
    UINT32 sev2_en : 1;
    /* sev2_en - Bits[2:2], RW, default = 1'b0 
       When set, the detection of error severity 2 generates system events.
     */
    UINT32 rsvd_3 : 29;
  } Bits;
  UINT32 Data;
} GSYSCTL_IIO_RAS_STRUCT;
#endif /* ASM_INC */






/* GFFERRST_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A1DC)                                                  */
/*       IVT_EX (0x4002A1DC)                                                  */
/*       HSX (0x4002A1DC)                                                     */
/*       BDX (0x4002A1DC)                                                     */
/* Register default value:              0x00000000                            */
#define GFFERRST_IIO_RAS_REG 0x090241DC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Fatal FERR Status.
 */
typedef union {
  struct {
    UINT32 log : 27;
    /* log - Bits[26:0], ROS_V, default = 27'b000000000000000000000000000 
       This field logs the global error status register content when the first fatal 
       error is reported. This has the same format as the global error status register 
       (GFERRST). 
     */
    UINT32 rsvd : 5;
    /* rsvd - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GFFERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */






/* GFNERRST_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A1E8)                                                  */
/*       IVT_EX (0x4002A1E8)                                                  */
/*       HSX (0x4002A1E8)                                                     */
/*       BDX (0x4002A1E8)                                                     */
/* Register default value:              0x00000000                            */
#define GFNERRST_IIO_RAS_REG 0x090241E8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Fatal NERR Status.
 */
typedef union {
  struct {
    UINT32 log : 27;
    /* log - Bits[26:0], ROS_V, default = 27'b000000000000000000000000000 
       This filed logs the global error status register content when the next fatal 
       error is reported. This has the same format as the global error status register 
       (GFERRST). 
     */
    UINT32 rsvd : 5;
    /* rsvd - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GFNERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* GNFERRST_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A1EC)                                                  */
/*       IVT_EX (0x4002A1EC)                                                  */
/*       HSX (0x4002A1EC)                                                     */
/*       BDX (0x4002A1EC)                                                     */
/* Register default value:              0x00000000                            */
#define GNFERRST_IIO_RAS_REG 0x090241EC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Non-Fatal FERR Status.
 */
typedef union {
  struct {
    UINT32 log : 27;
    /* log - Bits[26:0], ROS_V, default = 27'b000000000000000000000000000 
       This filed logs the global error status register content when the first 
       non-fatal error is reported. This has the same format as the global error status 
       register (GNERRST). 
     */
    UINT32 rsvd : 5;
    /* rsvd - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GNFERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */






/* GNNERRST_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A1F8)                                                  */
/*       IVT_EX (0x4002A1F8)                                                  */
/*       HSX (0x4002A1F8)                                                     */
/*       BDX (0x4002A1F8)                                                     */
/* Register default value:              0x00000000                            */
#define GNNERRST_IIO_RAS_REG 0x090241F8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Global Non-Fatal NERR Status.
 */
typedef union {
  struct {
    UINT32 log : 27;
    /* log - Bits[26:0], ROS_V, default = 27'b000000000000000000000000000 
       This filed logs the global error status register content when the subsequent 
       non-fatal error is reported. This has the same format as the global error status 
       register (GNERRST). 
     */
    UINT32 rsvd : 5;
    /* rsvd - Bits[31:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GNNERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0ERRST_IIO_RAS_REG supported on:                                       */
/*       IVT_EP (0x4002A230)                                                  */
/*       IVT_EX (0x4002A230)                                                  */
/*       HSX (0x4002A230)                                                     */
/*       BDX (0x4002A230)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0ERRST_IIO_RAS_REG 0x09024230


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Error Status.
 * This register indicates the error detected by the Coherent Interface.
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], RW1CS, default = 1'b0 
       Write Cache Correctable ECC (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], RW1CS, default = 1'b0 
       Write Cache Correctable ECC (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], RW1CS, default = 1'b0 
       Protocol Layer Received Poisoned Packet (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], RW1CS, default = 1'b0 
       Write Cache Un-correctable ECC (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], RW1CS, default = 1'b0 
       Write Cache Un-correctable ECC (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], RW1CS, default = 1'b0 
       CSR access crossing 32-bit boundary (Error Code 0xC3)
       
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], RW1CS, default = 1'b0 
       Protocol Layer Received Unexpected Response/Completion (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], RW1CS, default = 1'b0 
       Protocol Queue/Table Overflow or Underflow (Error Code 0xDA)
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], RW1CS, default = 1'b0 
       Protocol Parity Error (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0ERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Status.
 * This register indicates the error detected by the Coherent Interface.
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], RW1CS, default = 1'b0 
       Write Cache Correctable ECC (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], RW1CS, default = 1'b0 
       Write Cache Correctable ECC (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], RW1CS, default = 1'b0 
       Protocol Layer Received Poisoned Packet (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], RW1CS, default = 1'b0 
       Write Cache Un-correctable ECC (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], RW1CS, default = 1'b0 
       Write Cache Un-correctable ECC (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], RW1CS, default = 1'b0 
       CSR access crossing 32-bit boundary (Error Code 0xC3)
       
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], RW1CS, default = 1'b0 
       Protocol Layer Received Unexpected Response/Completion (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], RW1CS, default = 1'b0 
       Protocol Queue/Table Overflow or Underflow (Error Code 0xDA)
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], RW1CS, default = 1'b0 
       Protocol Parity Error (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch interface data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0ERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP0ERRCTL_IIO_RAS_REG supported on:                                      */
/*       IVT_EP (0x4002A234)                                                  */
/*       IVT_EX (0x4002A234)                                                  */
/*       HSX (0x4002A234)                                                     */
/*       BDX (0x4002A234)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0ERRCTL_IIO_RAS_REG 0x09024234


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Error Control.
 * This register enables the error status bit setting for a Coherent Interface 
 * detected error. Setting of the bit enables the setting of the corresponding 
 * error status bit in IRPPERRST register. If the bit is cleared, the corresponding 
 * error status will not be set. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], RWS, default = 1'b0 
       (Error Code 0xB4)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], RWS, default = 1'b0 
       (Error Code 0xB4)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], RWS, default = 1'b0 
       (Error Code 0xC1)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], RWS, default = 1'b0 
       (Error Code 0xC2)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], RWS, default = 1'b0 
       (Error Code 0xC2)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], RWS, default = 1'b0 
       (Error Code 0xC3)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], RWS, default = 1'b0 
       (Error Code 0xD7)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], RWS, default = 1'b0 
       (Error Code 0xDA)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], RWS, default = 1'b0 
       (Error Code 0xDB)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0ERRCTL_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Control.
 * This register enables the error status bit setting for a Coherent Interface 
 * detected error. Setting of the bit enables the setting of the corresponding 
 * error status bit in IRPPERRST register. If the bit is cleared, the corresponding 
 * error status will not be set. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], RWS, default = 1'b0 
       (Error Code 0xB4)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], RWS, default = 1'b0 
       (Error Code 0xB4)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], RWS, default = 1'b0 
       (Error Code 0xC1)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], RWS, default = 1'b0 
       (Error Code 0xC2)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], RWS, default = 1'b0 
       (Error Code 0xC2)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], RWS, default = 1'b0 
       (Error Code 0xC3)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], RWS, default = 1'b0 
       (Error Code 0xD7)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], RWS, default = 1'b0 
       (Error Code 0xDA)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], RWS, default = 1'b0 
       (Error Code 0xDB)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0ERRCTL_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP0FFERRST_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A238)                                                  */
/*       IVT_EX (0x4002A238)                                                  */
/*       HSX (0x4002A238)                                                     */
/*       BDX (0x4002A238)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0FFERRST_IIO_RAS_REG 0x09024238


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Status.
 * The error status log indicates which error is causing the report of the first 
 * fatal error event. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Used for queue/table overflow or underflow in coherent Interface protocol layer.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0FFERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Status.
 * The error status log indicates which error is causing the report of the first 
 * fatal error event. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Used for queue/table overflow or underflow in coherent Interface protocol layer.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0FFERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP0FNERRST_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A23C)                                                  */
/*       IVT_EX (0x4002A23C)                                                  */
/*       HSX (0x4002A23C)                                                     */
/*       BDX (0x4002A23C)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0FNERRST_IIO_RAS_REG 0x0902423C


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Fatal NERR Status.
 * The error status log indicates which error is causing the report of the next 
 * fatal error event (any event that is not the first). 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0FNERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal NERR Status.
 * The error status log indicates which error is causing the report of the next 
 * fatal error event (any event that is not the first). 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0FNERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP0FFERRHD0_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A240)                                                  */
/*       IVT_EX (0x4002A240)                                                  */
/*       HSX (0x4002A240)                                                     */
/*       BDX (0x4002A240)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0FFERRHD0_IIO_RAS_REG 0x09024240
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Header Log 0.
 * Header log stores the IIO data path header information of the associated IRP 
 * Protocol error. The header indicates where the error is originating from and the 
 * address of the cycle. The header information will be varies according the four 
 * error types: Message, Memory/IO Request, Configure Request and Completion. 
 * 
 * ***For the Message Type, the IRP Protocol Fatal FERR Header information as 
 * below: 
 * 127:96 MsgFields[63:32]: Message-Related Fields. This field is valid for 
 * messages only. These bits contain several message related fields as defined in 
 * the PCIe* specification. 
 * 95:64 MsgFields[31:0]: Message-Related Fields. This field is valid for messages 
 * only. These bits contain several message related fields as defined in the PCIe* 
 * specification. 
 * 63:56 MsgCode[7:0]: Message Code. This field is valid for message requests only. 
 * The message code encodings are as defined in the PCIe* specification. 
 * 47:32 ReqID[15:0]: Requester ID. This field is located here only for memory, 
 * configuration, I/O, and message requests. This field is located elsewhere for 
 * completions. This field in combination with the Tag field form a unique 
 * Transaction ID. The Requester ID is comprised as follows: {device[4:0], 
 * function[2:0], bus[7:0]}. The value from the original request must be preserved 
 * into the completion. 
 * 31:31 TD: TLP Digest. A value of 1 in this field indicates the presence of a 
 * single DW TLP digest at the end of the packet for use in ECRC protection as 
 * defined by the PCIe* specification.  
 * 30:30 EP: Error Poisoned. This field is used to indicate that the data payload 
 * contained in the packet is poisoned.  
 * 29:28 Attr[1:0]: Attributes. These provide hints as to how the packet should be 
 * handled: Bit 1 set to 1 indicates Relaxed Ordering, Bit 0 set to 1 indicates No 
 * Snoop. This field must be set to all 0 for configuration requests, I/O requests, 
 * message requests, and message signaled interrupts. 
 * 27:26 SwRID[6:5]: Switch Routing ID. This field is concatenated with SwRID[4:0] 
 * to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (i.e. 
 * these bit positions are reserved in the PCIe* spec.).This field facilitates 
 * routing of completions through the switch.  The upper five bits correspond to 
 * the switch port number assigned to the agent that originated the request and are 
 * used by the switch to route the completion. The lower two bits are provided for 
 * each agent to assign according to its own internal algorithm if needed for 
 * facilitating routing within the agent. The value in this field must be preserved 
 * from the original request requiring a completion and transferred into the 
 * completion. 
 * 25:16 Length[9:0]: Data Length. The data length is specified in DW (4-byte). For 
 * I/O and configuration requests, this field must be set to 1. This field is 
 * reserved for packets that do not contain or refer to data payloads. 
 * 15:15 MAbort: Master Abort Hint. This field is not part of the PCIe* spec. This 
 * field is used by the PCIe/DMI interface block to indicate that the switch 
 * should master abort a request; this would happen if the PCIe* block received an 
 * unsupported request. 
 * 14:12 TC[2:0]: Traffic Class. This allows differentiation of transactions into 
 * eight traffic service classes within the PCIe* interconnect fabric only. For I/O 
 * and configuration requests, this field must be set to all 0. 
 * 11:7 SwRID[4:0]: Switch Routing ID. This field is concatenated with SwRID[6:5] 
 * to form SwRID[6:0]. See description for SwRID[6:5]. 
 * 6:5 Fmt[1:0]: Format. This field combined with the Type field specifies the 
 * transaction type.  The encodings for valid {Fmt[1:0], Type[4:0]} combinations:  
 *    {2'b00, 5'b0_0000}: Memory Read  
 *    {2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
 *    {2'b00, 5'b0_0001}: Memory Read  Locked 
 *    {2'b01, 5'b0_0001}: Memory Read with extended address  Locked
 *    {2'b10, 5'b0_0000}: Memory Write 
 *    {2'b11, 5'b0_0000}: Memory Write with extended address 
 *    {2'b00, 5'b0_0010}: I/O Read 
 *    {2'b10, 5'b0_0010}: I/O Write 
 *    {2'b00, 5'b0_0100}: Configuration Read Type 0 
 *    {2'b10, 5'b0_0100}: Configuration Write Type 0 
 *    {2'b00, 5'b0_0101}: Configuration Read Type 1 
 *    {2'b10, 5'b0_0101}: Configuration Write  Type 1 
 *    {2'b00, 5'b1_1011}: Trusted Configuration Read 
 *    {2'b10, 5'b1_1011}: Trusted Configuration Write 
 *    {2'b00, 5'b0_1010}: Completion without Data 
 *    {2'b10, 5'b0_1010}: Completion with Data 
 *    {2'b00, 5'b0_1011}: Completion without Data  Locked 
 *    {2'b10, 5'b0_1011}: Completion with Data  Locked 
 *    {2'b01, 5'b1_0r2r1r0}: Message (r[2:0] are as defined in the PCIe* spec.) 
 *    {2'b11, 5'b1_0r2r1r0}: Message with Data 
 *    {2'b10, 5'b0_1100}: FetchAdd 
 *    {2'b11, 5'b0_1100}: FetchAdd 
 *    {2'b10, 5'b0_1101}: Swap 
 *    {2'b11, 5'b0_1101}: Swap 
 *    {2'b10, 5'b0_1110}: CAS 
 *    {2'b11, 5'b0_1110}: CAS
 * 4:0 Type[4:0]: Type. This field combined with the Format field specifies the 
 * transaction type. See the encodings in the description for the Fmt[1:0] field. 
 * 
 * ***For the Memory/IO Request Type, the IRP Protocol Fatal FERR Header 
 * information as below: 
 * 127:96 Addr[63:32]:Upper Address. This field is valid for 64-bit memory request 
 * only. This field should be set to all 0 for 32-bit memory requests, I/O 
 * requests, configuration requests, and completions. 
 * 95:66	Addr[31:2]: 32-bit Address.
 * 63:60 Last_DW_BE[3:0]:Last DW Byte Enables. This field is valid for memory, I/O, 
 * and configuration requests only. The value in this field is set to all 0 for I/O 
 * and configuration requests. 
 * 59:56 1st_DW_BE[3:0]: First DW Byte Enables. This field is valid for memory, I/O 
 * and configuration requests only. 
 * 55:48 Tag[7:0]: Tag. This field is valid for memory, I/O and configuration 
 * requests only. This field in combination with the Requester ID field form a 
 * unique Transaction ID. The value from the original request must be preserved 
 * into the completion. 
 * 47:32 ReqID[15:0]: Requester ID. This field is located here only for memory, 
 * configuration, I/O, and message requests. This field is located elsewhere for 
 * completions. This field in combination with the Tag field form a unique 
 * Transaction ID. The Requester ID is comprised as follows: {device[4:0], 
 * function[2:0], bus[7:0]}. The value from the original request must be preserved 
 * into the completion. 
 * 31:31 TD: TLP Digest. A value of 1 in this field indicates the presence of a 
 * single DW TLP digest at the end of the packet for use in ECRC protection as 
 * defined by the PCIe* specification.  
 * 30:30 EP: Error Poisoned. This field is used to indicate that the data payload 
 * contained in the packet is poisoned.  
 * 29:28 Attr[1:0]: Attributes. These provide hints as to how the packet should be 
 * handled: Bit 1 set to 1 indicates Relaxed Ordering, Bit 0 set to 1 indicates No 
 * Snoop. This field must be set to all 0 for configuration requests, I/O requests, 
 * message requests, and message signaled interrupts. 
 * 27:26 SwRID[6:5]: Switch Routing ID. This field is concatenated with SwRID[4:0] 
 * to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (i.e. 
 * these bit positions are reserved in the PCIe* spec.).This field facilitates 
 * routing of completions through the switch. The upper five bits correspond to the 
 * switch port number assigned to the agent that originated the request and are 
 * used by the switch to route the completion. The lower two bits are provided for 
 * each agent to assign according to its own internal algorithm if needed for 
 * facilitating routing within the agent.  The value in this field must be 
 * preserved from the original request requiring a completion and transferred into 
 * the completion. 
 * 25:16 Length[9:0]: Data Length. The data length is specified in DW (4-byte). For 
 * I/O and configuration requests, this field must be set to 1. This field is 
 * reserved for packets that do not contain or refer to data payloads. 
 * 15:15 MAbort: Master Abort Hint. This field is not part of the PCIe* spec. This 
 * field is used by the PCIe/DMI interface block to indicate that the switch 
 * should master abort a request; this would happen if the PCIe* block received an 
 * unsupported request. 
 * 14:12 TC[2:0]: Traffic Class. This allows differentiation of transactions into 
 * eight traffic service classes within the PCIe* interconnect fabric only. For I/O 
 * and configuration requests, this field must be set to all 0. 
 * 11:7 SwRID[4:0]: Switch Routing ID. This field is concatenated with SwRID[6:5] 
 * to form SwRID[6:0]. See description for SwRID[6:5]. 
 * 6:5 Fmt[1:0]: Format. This field combined with the Type field specifies the 
 * transaction type. The encodings for valid {Fmt[1:0], Type[4:0]} combinations:  
 *    {2'b00, 5'b0_0000}: Memory Read  
 *    {2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
 *    {2'b00, 5'b0_0001}: Memory Read  Locked 
 *    {2'b01, 5'b0_0001}: Memory Read with extended address  Locked
 *    {2'b10, 5'b0_0000}: Memory Write 
 *    {2'b11, 5'b0_0000}: Memory Write with extended address 
 *    {2'b00, 5'b0_0010}: I/O Read 
 *    {2'b10, 5'b0_0010}: I/O Write 
 *    {2'b00, 5'b0_0100}: Configuration Read Type 0 
 *    {2'b10, 5'b0_0100}: Configuration Write Type 0 
 *    {2'b00, 5'b0_0101}: Configuration Read Type 1 
 *    {2'b10, 5'b0_0101}: Configuration Write  Type 1 
 *    {2'b00, 5'b1_1011}: Trusted Configuration Read 
 *    {2'b10, 5'b1_1011}: Trusted Configuration Write 
 *    {2'b00, 5'b0_1010}: Completion without Data 
 *    {2'b10, 5'b0_1010}: Completion with Data 
 *    {2'b00, 5'b0_1011}: Completion without Data  Locked 
 *    {2'b10, 5'b0_1011}: Completion with Data  Locked 
 *    {2'b01, 5'b1_0r2r1r0}: Message (r[2:0] as defined in the PCIe* spec.) 
 *    {2'b11, 5'b1_0r2r1r0}: Message with Data 
 *    {2'b10, 5'b0_1100}: FetchAdd 
 *    {2'b11, 5'b0_1100}: FetchAdd 
 *    {2'b10, 5'b0_1101}: Swap 
 *    {2'b11, 5'b0_1101}: Swap 
 *    {2'b10, 5'b0_1110}: CAS 
 *    {2'b11, 5'b0_1110}: CAS
 * 4:0 Type[4:0]: Type. This field combined with the Format field specifies the 
 * transaction type. See the encodings in the description for the Fmt[1:0] field. 
 * 
 * ***For the Configuration Request Type, the IRP Protocol Fatal FERR Header 
 * information as below: 
 * 127:96 Addr[63:32]: Upper Address. This field is valid for 64-bit memory request 
 * only. This field should be set to all 0 for 32-bit memory requests, I/O 
 * requests, configuration requests, and completions. 
 * 95:90 Reg[5:0]: Register Number. This field is valid for configuration requests 
 * only. 
 * 83:80 ExtReg[3:0]: Extended Register Number. This field is valid for 
 * configuration requests only. 
 * 79:64 RouteID[15:0]: ID Routing Fields. This field is valid for configuration 
 * requests only. This contains information to route the packet to the target and 
 * is comprised as follows: {device[4:0], function[2:0], bus[7:0]} 
 * 63:60 Last_DW_BE[3:0]: Last DW Byte Enables. This field is valid for memory, 
 * I/O, and configuration requests only. The value in this field is set to all 0 
 * for I/O and configuration requests. 
 * 59:56 1st_DW_BE[3:0]: First DW Byte Enables. This field is valid for memory, I/O 
 * and configuration requests only. 
 * 55:48 Tag[7:0]: Tag. This field is valid for memory, I/O and configuration 
 * requests only. This field in combination with the Requester ID field form a 
 * unique Transaction ID. The value from the original request must be preserved 
 * into the completion. 
 * 47:32 ReqID[15:0]: Requester ID. This field is located here only for memory, 
 * configuration, I/O, and message requests. This field is located elsewhere for 
 * completions. This field in combination with the Tag field form a unique 
 * Transaction ID. The Requester ID is comprised as follows: {device[4:0], 
 * function[2:0], bus[7:0]}. The value from the original request must be preserved 
 * into the completion. 
 * 31:31 TD: TLP Digest. A value of 1 in this field indicates the presence of a 
 * single DW TLP digest at the end of the packet for use in ECRC protection as 
 * defined by the PCIe* specification.  
 * 30:30 EP: Error Poisoned. This field is used to indicate that the data payload 
 * contained in the packet is poisoned.  
 * 29:28 Attr[1:0]: Attributes. These provide hints as to how the packet should be 
 * handled: Bit 1 set to 1 indicates Relaxed Ordering, Bit 0 set to 1 indicates No 
 * Snoop. This field must be set to all 0 for configuration requests, I/O requests, 
 * message requests, and message signaled interrupts.  
 * 27:26 SwRID[6:5]: Switch Routing ID. This field is concatenated with SwRID[4:0] 
 * to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (i.e. 
 * these bit positions are reserved in the PCIe* spec.).This field facilitates 
 * routing of completions through the switch. The upper five bits correspond to the 
 * switch port number assigned to the agent that originated the request and are 
 * used by the switch to route the completion. The lower two bits are provided for 
 * each agent to assign according to its own internal algorithm if needed for 
 * facilitating routing within the agent. The value in this field must be preserved 
 * from the original request requiring a completion and transferred into the 
 * completion. 
 * 25:16 Length[9:0]: Data Length. The data length is specified in DW (4-byte). For 
 * I/O and configuration requests, this field must be set to 1. This field is 
 * reserved for packets that do not contain or refer to data payloads. 
 * 15:15 MAbort: Master Abort Hint. This field is not part of the PCIe* spec. This 
 * field is used by the PCIe/DMI interface block to indicate that the switch 
 * should master abort a request; this would happen if the PCIe* block received an 
 * unsupported request. 
 * 14:12 TC[2:0]: Traffic Class. This allows differentiation of transactions into 
 * eight traffic service classes within the PCIe* interconnect fabric only. For I/O 
 * and configuration requests, this field must be set to all 0. 
 * 11:7 SwRID[4:0]: Switch Routing ID. This field is concatenated with SwRID[6:5] 
 * to form SwRID[6:0]. See description for SwRID[6:5]. 
 * 6:5 Fmt[1:0]: Format. This field combined with the Type field specifies the 
 * transaction type. The encodings for valid {Fmt[1:0], Type[4:0]} combinations:  
 *    {2'b00, 5'b0_0000}: Memory Read  
 *    {2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
 *    {2'b00, 5'b0_0001}: Memory Read  Locked 
 *    {2'b01, 5'b0_0001}: Memory Read with extended address  Locked
 *    {2'b10, 5'b0_0000}: Memory Write 
 *    {2'b11, 5'b0_0000}: Memory Write with extended address 
 *    {2'b00, 5'b0_0010}: I/O Read 
 *    {2'b10, 5'b0_0010}: I/O Write 
 *    {2'b00, 5'b0_0100}: Configuration Read Type 0 
 *    {2'b10, 5'b0_0100}: Configuration Write Type 0 
 *    {2'b00, 5'b0_0101}: Configuration Read Type 1 
 *    {2'b10, 5'b0_0101}: Configuration Write  Type 1 
 *    {2'b00, 5'b1_1011}: Trusted Configuration Read 
 *    {2'b10, 5'b1_1011}: Trusted Configuration Write 
 *    {2'b00, 5'b0_1010}: Completion without Data 
 *    {2'b10, 5'b0_1010}: Completion with Data 
 *    {2'b00, 5'b0_1011}: Completion without Data  Locked 
 *    {2'b10, 5'b0_1011}: Completion with Data  Locked 
 *    {2'b01, 5'b1_0r2r1r0}: Message (r[2:0] are as defined in the PCIe* spec.) 
 *    {2'b11, 5'b1_0r2r1r0}: Message with Data 
 *    {2'b10, 5'b0_1100}: FetchAdd 
 *    {2'b11, 5'b0_1100}: FetchAdd 
 *    {2'b10, 5'b0_1101}: Swap 
 *    {2'b11, 5'b0_1101}: Swap 
 *    {2'b10, 5'b0_1110}: CAS 
 *    {2'b11, 5'b0_1110}: CAS
 * 4:0 Type[4:0]: Type. This field combined with the Format field specifies the 
 * transaction type. See the encodings in the description for the Fmt[1:0] field. 
 * 
 * ***For the Completion Type, the IRP Protocol Fatal FERR Header information as 
 * below: 
 * 127:96 Addr[63:32]: Upper Address. This field is valid for 64-bit memory request 
 * only. This field should be set to all 0 for 32-bit memory requests, I/O 
 * requests, configuration requests, and completions. 
 * 94:88 Lower_Address[6:0]: Lower Address. This field is valid for completions 
 * only. For memory read completions, this is the byte address for the first 
 * enabled byte of data returned. For all other completions, this field is set to 
 * all 0. 
 * 87:80 Tag[7:0]: Tag. This field is valid for completions only. This field in 
 * combination with the Requester ID field form a unique Transaction ID. The value 
 * from the original request must be preserved into the completion. 
 * 79:64 ReqID[15:0]: Requester ID. This field is located here for completions 
 * only. It is located elsewhere for memory, configuration, I/O, and message 
 * requests. This field in combination with the Tag field form a unique Transaction 
 * ID. The Requester ID is comprised as follows: {device[4:0], function[2:0], 
 * bus[7:0]}. The value from the original request must be preserved into the 
 * completion. 
 * 63:56 ByteCnt[7:0]: Byte Count. This field is valid for completions only. For 
 * memory read completions, this specifies the remaining byte count to satisfy the 
 * request including the current packet payload. For all other completions, this 
 * field must be set to 4. This field is concatenated with ByteCnt[11:8] to form 
 * ByteCnt[11:0]. 
 * 55:53 CplStat[2:0]: Completion Status. This field is valid for completions only. 
 * This indicates the status for the completion, encoded as follows:  
 *    3'b000: Successful Completion 
 *    3'b001: Unsupported Request/Master Abort 
 *    3'b010: Configuration Request Retry Status 
 *    3'b100: Completer Abort 
 *    All other encodings are reserved.
 * 52:52 BCM: Byte Count Modified. This field is valid for completions only. This 
 * field is set only in initial completion packets and only by PCI-X completer. A 
 * value of 1 indicates that the Byte Count field reports only the size of the 
 * current packet. 
 * 51:48 ByteCnt[11:8]: Byte Count. This field is valid for completions only. This 
 * field is concatenated with ByteCnt[7:0] to form ByteCnt[11:0]. See description 
 * for ByteCnt[7:0]. 
 * 47:32 CplID[15:0]: Completer ID. This field is valid for completions only. This 
 * uniquely identifies the completer and is comprised as follows: {device[4:0], 
 * function[2:0], bus[7:0]}. 
 * 31:31 TD: TLP Digest. A value of 1 in this field indicates the presence of a 
 * single DW TLP digest at the end of the packet for use in ECRC protection as 
 * defined by the PCIe* specification.  
 * 30:30 EP: Error Poisoned. This field is used to indicate that the data payload 
 * contained in the packet is poisoned.  
 * 29:28 Attr[1:0]: Attributes. These provide hints as to how the packet should be 
 * handled: Bit 1 set to 1 indicates Relaxed Ordering, Bit 0 set to 1 indicates No 
 * Snoop. This field must be set to all 0 for configuration requests, I/O requests, 
 * message requests, and message signaled interrupts. 
 * 27:26 SwRID[6:5]: Switch Routing ID. This field is concatenated with SwRID[4:0] 
 * to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (i.e. 
 * these bit positions are reserved in the PCIe* spec.).This field facilitates 
 * routing of completions through the switch. The upper five bits correspond to the 
 * switch port number assigned to the agent that originated the request and are 
 * used by the switch to route the completion. The lower two bits are provided for 
 * each agent to assign according to its own internal algorithm if needed for 
 * facilitating routing within the agent. The value in this field must be preserved 
 * from the original request requiring a completion and transferred into the 
 * completion. 
 * 25:16 Length[9:0]: Data Length. The data length is specified in DW (4-byte). For 
 * I/O and configuration requests, this field must be set to 1. This field is 
 * reserved for packets that do not contain or refer to data payloads. 
 * 15:15 MAbort: Master Abort Hint. This field is not part of the PCIe* spec. This 
 * field is used by the PCIe/DMI interface block to indicate that the switch 
 * should master abort a request; this would happen if the PCIe* block received an 
 * unsupported request. 
 * 14:12 TC[2:0]: Traffic Class. This allows differentiation of transactions into 
 * eight traffic service classes within the PCIe* interconnect fabric only. For I/O 
 * and configuration requests, this field must be set to all 0. 
 * 11:7 SwRID[4:0]: Switch Routing ID. This field is concatenated with SwRID[6:5] 
 * to form SwRID[6:0]. See description for SwRID[6:5]. 
 * 6:5 Fmt[1:0]: Format. This field combined with the Type field specifies the 
 * transaction type.                   The encodings for valid {Fmt[1:0], 
 * Type[4:0]} combinations:  
 *    {2'b00, 5'b0_0000}: Memory Read  
 *    {2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
 *    {2'b00, 5'b0_0001}: Memory Read  Locked 
 *    {2'b01, 5'b0_0001}: Memory Read with extended address  Locked
 *    {2'b10, 5'b0_0000}: Memory Write 
 *    {2'b11, 5'b0_0000}: Memory Write with extended address 
 *    {2'b00, 5'b0_0010}: I/O Read 
 *    {2'b10, 5'b0_0010}: I/O Write 
 *    {2'b00, 5'b0_0100}: Configuration Read Type 0 
 *    {2'b10, 5'b0_0100}: Configuration Write Type 0 
 *    {2'b00, 5'b0_0101}: Configuration Read Type 1 
 *    {2'b10, 5'b0_0101}: Configuration Write  Type 1 
 *    {2'b00, 5'b1_1011}: Trusted Configuration Read 
 *    {2'b10, 5'b1_1011}: Trusted Configuration Write 
 *    {2'b00, 5'b0_1010}: Completion without Data 
 *    {2'b10, 5'b0_1010}: Completion with Data 
 *    {2'b00, 5'b0_1011}: Completion without Data  Locked 
 *    {2'b10, 5'b0_1011}: Completion with Data  Locked 
 *    {2'b01, 5'b1_0r2r1r0}: Message (r[2:0] are as defined in the PCIe* spec.) 
 *    {2'b11, 5'b1_0r2r1r0}: Message with Data 
 *    {2'b10, 5'b0_1100}: FetchAdd 
 *    {2'b11, 5'b0_1100}: FetchAdd 
 *    {2'b10, 5'b0_1101}: Swap 
 *    {2'b11, 5'b0_1101}: Swap 
 *    {2'b10, 5'b0_1110}: CAS 
 *    {2'b11, 5'b0_1110}: CAS
 * 4:0 Type[4:0]: Type. This field combined with the Format field specifies the 
 * transaction type. See the encodings in the description for the Fmt[1:0] field. 
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the first DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP0FFERRHD0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0FFERRHD1_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A244)                                                  */
/*       IVT_EX (0x4002A244)                                                  */
/*       HSX (0x4002A244)                                                     */
/*       BDX (0x4002A244)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0FFERRHD1_IIO_RAS_REG 0x09024244
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Header Log 1.
 * Refer to IRPPxFFERRHD0 for details.
 * 
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the second DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP0FFERRHD1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0FFERRHD2_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A248)                                                  */
/*       IVT_EX (0x4002A248)                                                  */
/*       HSX (0x4002A248)                                                     */
/*       BDX (0x4002A248)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0FFERRHD2_IIO_RAS_REG 0x09024248
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Header Log 2.
 * Refer to IRPPxFFERRHD0 for details.
 * 
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the third DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP0FFERRHD2_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0FFERRHD3_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A24C)                                                  */
/*       IVT_EX (0x4002A24C)                                                  */
/*       HSX (0x4002A24C)                                                     */
/*       BDX (0x4002A24C)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0FFERRHD3_IIO_RAS_REG 0x0902424C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Header Log 3.
 * Refer to IRPPxFFERRHD0 for details.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the fourth DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP0FFERRHD3_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0NFERRST_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A250)                                                  */
/*       IVT_EX (0x4002A250)                                                  */
/*       HSX (0x4002A250)                                                     */
/*       BDX (0x4002A250)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0NFERRST_IIO_RAS_REG 0x09024250


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal First Error.
 * The error status log indicates which error is causing the report of the first 
 * non-fatal error event. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
       
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0NFERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal First Error.
 * The error status log indicates which error is causing the report of the first 
 * non-fatal error event. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
       
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0NFERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP0NNERRST_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A254)                                                  */
/*       IVT_EX (0x4002A254)                                                  */
/*       HSX (0x4002A254)                                                     */
/*       BDX (0x4002A254)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0NNERRST_IIO_RAS_REG 0x09024254


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal NERR Status.
 * The error status log indicates which error is causing the report of the next 
 * non-fatal error event (any event that is not the first). 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0NNERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal NERR Status.
 * The error status log indicates which error is causing the report of the next 
 * non-fatal error event (any event that is not the first). 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0NNERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP0NFERRHD0_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A258)                                                  */
/*       IVT_EX (0x4002A258)                                                  */
/*       HSX (0x4002A258)                                                     */
/*       BDX (0x4002A258)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0NFERRHD0_IIO_RAS_REG 0x09024258
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal FERR Header Log 0.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the first DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP0NFERRHD0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0NFERRHD1_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A25C)                                                  */
/*       IVT_EX (0x4002A25C)                                                  */
/*       HSX (0x4002A25C)                                                     */
/*       BDX (0x4002A25C)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0NFERRHD1_IIO_RAS_REG 0x0902425C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal FERR Header Log 1.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the second DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP0NFERRHD1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0NFERRHD2_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A260)                                                  */
/*       IVT_EX (0x4002A260)                                                  */
/*       HSX (0x4002A260)                                                     */
/*       BDX (0x4002A260)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0NFERRHD2_IIO_RAS_REG 0x09024260
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal FERR Header Log 2.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the third DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP0NFERRHD2_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0NFERRHD3_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A264)                                                  */
/*       IVT_EX (0x4002A264)                                                  */
/*       HSX (0x4002A264)                                                     */
/*       BDX (0x4002A264)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0NFERRHD3_IIO_RAS_REG 0x09024264
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal FERR Header Log 3.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the fourth DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP0NFERRHD3_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0ERRCNTSEL_IIO_RAS_REG supported on:                                   */
/*       IVT_EP (0x4002A268)                                                  */
/*       IVT_EX (0x4002A268)                                                  */
/*       HSX (0x4002A268)                                                     */
/*       BDX (0x4002A268)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0ERRCNTSEL_IIO_RAS_REG 0x09024268
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Counter Select.
 */
typedef union {
  struct {
    UINT32 irp_error_count_select : 19;
    /* irp_error_count_select - Bits[18:0], RW, default = 19'b0000000000000000000 
       See IRPP0ERRST for per bit description of each error. Each bit in this field has 
       the following behavior: 
       0: Do not select this error type for error counting
       1: Select this error type for error counting
     */
    UINT32 rsvd : 13;
    /* rsvd - Bits[31:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0ERRCNTSEL_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP0ERRCNT_IIO_RAS_REG supported on:                                      */
/*       IVT_EP (0x4002A26C)                                                  */
/*       IVT_EX (0x4002A26C)                                                  */
/*       HSX (0x4002A26C)                                                     */
/*       BDX (0x4002A26C)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP0ERRCNT_IIO_RAS_REG 0x0902426C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Count.
 */
typedef union {
  struct {
    UINT32 errcnt : 7;
    /* errcnt - Bits[6:0], RW1CS, default = 7'b0000000 
       This counter accumulates errors that occur when the associated error type is 
       selected in the ERRCNTSEL register. 
       
       Notes:
       This register is cleared by writing 7Fh.
       Maximum counter available is 127d (7Fh)
     */
    UINT32 errovf : 1;
    /* errovf - Bits[7:7], RW1CS, default = 1'b0 
       Error Accumulator Overflow
       0: No overflow occurred
       1: Error overflow. The error count may not be valid.
     */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP0ERRCNT_IIO_RAS_STRUCT;
#endif /* ASM_INC */








/* IRPP1ERRST_IIO_RAS_REG supported on:                                       */
/*       IVT_EP (0x4002A2B0)                                                  */
/*       IVT_EX (0x4002A2B0)                                                  */
/*       HSX (0x4002A2B0)                                                     */
/*       BDX (0x4002A2B0)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1ERRST_IIO_RAS_REG 0x090242B0


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Error Status.
 * This register indicates the error detected by the Coherent Interface.
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], RW1CS, default = 1'b0 
       Write Cache Correctable ECC (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], RW1CS, default = 1'b0 
       Write Cache Correctable ECC (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], RW1CS, default = 1'b0 
       Protocol Layer Received Poisoned Packet (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], RW1CS, default = 1'b0 
       Write Cache Un-correctable ECC (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], RW1CS, default = 1'b0 
       Write Cache Un-correctable ECC (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], RW1CS, default = 1'b0 
       CSR access crossing 32-bit boundary (Error Code 0xC3)
       
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], RW1CS, default = 1'b0 
       Protocol Layer Received Unexpected Response/Completion (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], RW1CS, default = 1'b0 
       Protocol Queue/Table Overflow or Underflow (Error Code 0xDA)
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], RW1CS, default = 1'b0 
       Protocol Parity Error (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1ERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Status.
 * This register indicates the error detected by the Coherent Interface.
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], RW1CS, default = 1'b0 
       Write Cache Correctable ECC (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], RW1CS, default = 1'b0 
       Write Cache Correctable ECC (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], RW1CS, default = 1'b0 
       Protocol Layer Received Poisoned Packet (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], RW1CS, default = 1'b0 
       Write Cache Un-correctable ECC (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], RW1CS, default = 1'b0 
       Write Cache Un-correctable ECC (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], RW1CS, default = 1'b0 
       CSR access crossing 32-bit boundary (Error Code 0xC3)
       
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], RW1CS, default = 1'b0 
       Protocol Layer Received Unexpected Response/Completion (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], RW1CS, default = 1'b0 
       Protocol Queue/Table Overflow or Underflow (Error Code 0xDA)
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], RW1CS, default = 1'b0 
       Protocol Parity Error (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch interface data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1ERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP1ERRCTL_IIO_RAS_REG supported on:                                      */
/*       IVT_EP (0x4002A2B4)                                                  */
/*       IVT_EX (0x4002A2B4)                                                  */
/*       HSX (0x4002A2B4)                                                     */
/*       BDX (0x4002A2B4)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1ERRCTL_IIO_RAS_REG 0x090242B4


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Error Control.
 * This register enables the error status bit setting for a Coherent Interface 
 * detected error. Setting of the bit enables the setting of the corresponding 
 * error status bit in IRPPERRST register. If the bit is cleared, the corresponding 
 * error status will not be set. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], RWS, default = 1'b0 
       (Error Code 0xB4)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], RWS, default = 1'b0 
       (Error Code 0xB4)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], RWS, default = 1'b0 
       (Error Code 0xC1)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], RWS, default = 1'b0 
       (Error Code 0xC2)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], RWS, default = 1'b0 
       (Error Code 0xC2)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], RWS, default = 1'b0 
       (Error Code 0xC3)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], RWS, default = 1'b0 
       (Error Code 0xD7)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], RWS, default = 1'b0 
       (Error Code 0xDA)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], RWS, default = 1'b0 
       (Error Code 0xDB)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1ERRCTL_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Control.
 * This register enables the error status bit setting for a Coherent Interface 
 * detected error. Setting of the bit enables the setting of the corresponding 
 * error status bit in IRPPERRST register. If the bit is cleared, the corresponding 
 * error status will not be set. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], RWS, default = 1'b0 
       (Error Code 0xB4)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], RWS, default = 1'b0 
       (Error Code 0xB4)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], RWS, default = 1'b0 
       (Error Code 0xC1)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], RWS, default = 1'b0 
       (Error Code 0xC2)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], RWS, default = 1'b0 
       (Error Code 0xC2)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], RWS, default = 1'b0 
       (Error Code 0xC3)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], RWS, default = 1'b0 
       (Error Code 0xD7)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], RWS, default = 1'b0 
       (Error Code 0xDA)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], RWS, default = 1'b0 
       (Error Code 0xDB)
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RWS, default = 1'b0 
       0: Disable error status logging for this error
       1: Enable Error status logging for this error
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1ERRCTL_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP1FFERRST_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A2B8)                                                  */
/*       IVT_EX (0x4002A2B8)                                                  */
/*       HSX (0x4002A2B8)                                                     */
/*       BDX (0x4002A2B8)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1FFERRST_IIO_RAS_REG 0x090242B8


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Status.
 * The error status log indicates which error is causing the report of the first 
 * fatal error event. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Used for queue/table overflow or underflow in coherent Interface protocol layer.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1FFERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Status.
 * The error status log indicates which error is causing the report of the first 
 * fatal error event. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Used for queue/table overflow or underflow in coherent Interface protocol layer.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1FFERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP1FNERRST_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A2BC)                                                  */
/*       IVT_EX (0x4002A2BC)                                                  */
/*       HSX (0x4002A2BC)                                                     */
/*       BDX (0x4002A2BC)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1FNERRST_IIO_RAS_REG 0x090242BC


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Fatal NERR Status.
 * The error status log indicates which error is causing the report of the next 
 * fatal error event (any event that is not the first). 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1FNERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal NERR Status.
 * The error status log indicates which error is causing the report of the next 
 * fatal error event (any event that is not the first). 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1FNERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP1FFERRHD0_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A2C0)                                                  */
/*       IVT_EX (0x4002A2C0)                                                  */
/*       HSX (0x4002A2C0)                                                     */
/*       BDX (0x4002A2C0)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1FFERRHD0_IIO_RAS_REG 0x090242C0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Header Log 0.
 * Header log stores the IIO data path header information of the associated IRP 
 * Protocol error. The header indicates where the error is originating from and the 
 * address of the cycle. The header information will be varies according the four 
 * error types: Message, Memory/IO Request, Configure Request and Completion. 
 * 
 * ***For the Message Type, the IRP Protocol Fatal FERR Header information as 
 * below: 
 * 127:96 MsgFields[63:32]: Message-Related Fields. This field is valid for 
 * messages only. These bits contain several message related fields as defined in 
 * the PCIe* specification. 
 * 95:64 MsgFields[31:0]: Message-Related Fields. This field is valid for messages 
 * only. These bits contain several message related fields as defined in the PCIe* 
 * specification. 
 * 63:56 MsgCode[7:0]: Message Code. This field is valid for message requests only. 
 * The message code encodings are as defined in the PCIe* specification. 
 * 47:32 ReqID[15:0]: Requester ID. This field is located here only for memory, 
 * configuration, I/O, and message requests. This field is located elsewhere for 
 * completions. This field in combination with the Tag field form a unique 
 * Transaction ID. The Requester ID is comprised as follows: {device[4:0], 
 * function[2:0], bus[7:0]}. The value from the original request must be preserved 
 * into the completion. 
 * 31:31 TD: TLP Digest. A value of 1 in this field indicates the presence of a 
 * single DW TLP digest at the end of the packet for use in ECRC protection as 
 * defined by the PCIe* specification.  
 * 30:30 EP: Error Poisoned. This field is used to indicate that the data payload 
 * contained in the packet is poisoned.  
 * 29:28 Attr[1:0]: Attributes. These provide hints as to how the packet should be 
 * handled: Bit 1 set to 1 indicates Relaxed Ordering, Bit 0 set to 1 indicates No 
 * Snoop. This field must be set to all 0 for configuration requests, I/O requests, 
 * message requests, and message signaled interrupts. 
 * 27:26 SwRID[6:5]: Switch Routing ID. This field is concatenated with SwRID[4:0] 
 * to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (i.e. 
 * these bit positions are reserved in the PCIe* spec.).This field facilitates 
 * routing of completions through the switch.  The upper five bits correspond to 
 * the switch port number assigned to the agent that originated the request and are 
 * used by the switch to route the completion. The lower two bits are provided for 
 * each agent to assign according to its own internal algorithm if needed for 
 * facilitating routing within the agent. The value in this field must be preserved 
 * from the original request requiring a completion and transferred into the 
 * completion. 
 * 25:16 Length[9:0]: Data Length. The data length is specified in DW (4-byte). For 
 * I/O and configuration requests, this field must be set to 1. This field is 
 * reserved for packets that do not contain or refer to data payloads. 
 * 15:15 MAbort: Master Abort Hint. This field is not part of the PCIe* spec. This 
 * field is used by the PCIe/DMI interface block to indicate that the switch 
 * should master abort a request; this would happen if the PCIe* block received an 
 * unsupported request. 
 * 14:12 TC[2:0]: Traffic Class. This allows differentiation of transactions into 
 * eight traffic service classes within the PCIe* interconnect fabric only. For I/O 
 * and configuration requests, this field must be set to all 0. 
 * 11:7 SwRID[4:0]: Switch Routing ID. This field is concatenated with SwRID[6:5] 
 * to form SwRID[6:0]. See description for SwRID[6:5]. 
 * 6:5 Fmt[1:0]: Format. This field combined with the Type field specifies the 
 * transaction type.  The encodings for valid {Fmt[1:0], Type[4:0]} combinations:  
 *    {2'b00, 5'b0_0000}: Memory Read  
 *    {2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
 *    {2'b00, 5'b0_0001}: Memory Read  Locked 
 *    {2'b01, 5'b0_0001}: Memory Read with extended address  Locked
 *    {2'b10, 5'b0_0000}: Memory Write 
 *    {2'b11, 5'b0_0000}: Memory Write with extended address 
 *    {2'b00, 5'b0_0010}: I/O Read 
 *    {2'b10, 5'b0_0010}: I/O Write 
 *    {2'b00, 5'b0_0100}: Configuration Read Type 0 
 *    {2'b10, 5'b0_0100}: Configuration Write Type 0 
 *    {2'b00, 5'b0_0101}: Configuration Read Type 1 
 *    {2'b10, 5'b0_0101}: Configuration Write  Type 1 
 *    {2'b00, 5'b1_1011}: Trusted Configuration Read 
 *    {2'b10, 5'b1_1011}: Trusted Configuration Write 
 *    {2'b00, 5'b0_1010}: Completion without Data 
 *    {2'b10, 5'b0_1010}: Completion with Data 
 *    {2'b00, 5'b0_1011}: Completion without Data  Locked 
 *    {2'b10, 5'b0_1011}: Completion with Data  Locked 
 *    {2'b01, 5'b1_0r2r1r0}: Message (r[2:0] are as defined in the PCIe* spec.) 
 *    {2'b11, 5'b1_0r2r1r0}: Message with Data 
 *    {2'b10, 5'b0_1100}: FetchAdd 
 *    {2'b11, 5'b0_1100}: FetchAdd 
 *    {2'b10, 5'b0_1101}: Swap 
 *    {2'b11, 5'b0_1101}: Swap 
 *    {2'b10, 5'b0_1110}: CAS 
 *    {2'b11, 5'b0_1110}: CAS
 * 4:0 Type[4:0]: Type. This field combined with the Format field specifies the 
 * transaction type. See the encodings in the description for the Fmt[1:0] field. 
 * 
 * ***For the Memory/IO Request Type, the IRP Protocol Fatal FERR Header 
 * information as below: 
 * 127:96 Addr[63:32]:Upper Address. This field is valid for 64-bit memory request 
 * only. This field should be set to all 0 for 32-bit memory requests, I/O 
 * requests, configuration requests, and completions. 
 * 95:66	Addr[31:2]: 32-bit Address.
 * 63:60 Last_DW_BE[3:0]:Last DW Byte Enables. This field is valid for memory, I/O, 
 * and configuration requests only. The value in this field is set to all 0 for I/O 
 * and configuration requests. 
 * 59:56 1st_DW_BE[3:0]: First DW Byte Enables. This field is valid for memory, I/O 
 * and configuration requests only. 
 * 55:48 Tag[7:0]: Tag. This field is valid for memory, I/O and configuration 
 * requests only. This field in combination with the Requester ID field form a 
 * unique Transaction ID. The value from the original request must be preserved 
 * into the completion. 
 * 47:32 ReqID[15:0]: Requester ID. This field is located here only for memory, 
 * configuration, I/O, and message requests. This field is located elsewhere for 
 * completions. This field in combination with the Tag field form a unique 
 * Transaction ID. The Requester ID is comprised as follows: {device[4:0], 
 * function[2:0], bus[7:0]}. The value from the original request must be preserved 
 * into the completion. 
 * 31:31 TD: TLP Digest. A value of 1 in this field indicates the presence of a 
 * single DW TLP digest at the end of the packet for use in ECRC protection as 
 * defined by the PCIe* specification.  
 * 30:30 EP: Error Poisoned. This field is used to indicate that the data payload 
 * contained in the packet is poisoned.  
 * 29:28 Attr[1:0]: Attributes. These provide hints as to how the packet should be 
 * handled: Bit 1 set to 1 indicates Relaxed Ordering, Bit 0 set to 1 indicates No 
 * Snoop. This field must be set to all 0 for configuration requests, I/O requests, 
 * message requests, and message signaled interrupts. 
 * 27:26 SwRID[6:5]: Switch Routing ID. This field is concatenated with SwRID[4:0] 
 * to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (i.e. 
 * these bit positions are reserved in the PCIe* spec.).This field facilitates 
 * routing of completions through the switch. The upper five bits correspond to the 
 * switch port number assigned to the agent that originated the request and are 
 * used by the switch to route the completion. The lower two bits are provided for 
 * each agent to assign according to its own internal algorithm if needed for 
 * facilitating routing within the agent.  The value in this field must be 
 * preserved from the original request requiring a completion and transferred into 
 * the completion. 
 * 25:16 Length[9:0]: Data Length. The data length is specified in DW (4-byte). For 
 * I/O and configuration requests, this field must be set to 1. This field is 
 * reserved for packets that do not contain or refer to data payloads. 
 * 15:15 MAbort: Master Abort Hint. This field is not part of the PCIe* spec. This 
 * field is used by the PCIe/DMI interface block to indicate that the switch 
 * should master abort a request; this would happen if the PCIe* block received an 
 * unsupported request. 
 * 14:12 TC[2:0]: Traffic Class. This allows differentiation of transactions into 
 * eight traffic service classes within the PCIe* interconnect fabric only. For I/O 
 * and configuration requests, this field must be set to all 0. 
 * 11:7 SwRID[4:0]: Switch Routing ID. This field is concatenated with SwRID[6:5] 
 * to form SwRID[6:0]. See description for SwRID[6:5]. 
 * 6:5 Fmt[1:0]: Format. This field combined with the Type field specifies the 
 * transaction type. The encodings for valid {Fmt[1:0], Type[4:0]} combinations:  
 *    {2'b00, 5'b0_0000}: Memory Read  
 *    {2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
 *    {2'b00, 5'b0_0001}: Memory Read  Locked 
 *    {2'b01, 5'b0_0001}: Memory Read with extended address  Locked
 *    {2'b10, 5'b0_0000}: Memory Write 
 *    {2'b11, 5'b0_0000}: Memory Write with extended address 
 *    {2'b00, 5'b0_0010}: I/O Read 
 *    {2'b10, 5'b0_0010}: I/O Write 
 *    {2'b00, 5'b0_0100}: Configuration Read Type 0 
 *    {2'b10, 5'b0_0100}: Configuration Write Type 0 
 *    {2'b00, 5'b0_0101}: Configuration Read Type 1 
 *    {2'b10, 5'b0_0101}: Configuration Write  Type 1 
 *    {2'b00, 5'b1_1011}: Trusted Configuration Read 
 *    {2'b10, 5'b1_1011}: Trusted Configuration Write 
 *    {2'b00, 5'b0_1010}: Completion without Data 
 *    {2'b10, 5'b0_1010}: Completion with Data 
 *    {2'b00, 5'b0_1011}: Completion without Data  Locked 
 *    {2'b10, 5'b0_1011}: Completion with Data  Locked 
 *    {2'b01, 5'b1_0r2r1r0}: Message (r[2:0] as defined in the PCIe* spec.) 
 *    {2'b11, 5'b1_0r2r1r0}: Message with Data 
 *    {2'b10, 5'b0_1100}: FetchAdd 
 *    {2'b11, 5'b0_1100}: FetchAdd 
 *    {2'b10, 5'b0_1101}: Swap 
 *    {2'b11, 5'b0_1101}: Swap 
 *    {2'b10, 5'b0_1110}: CAS 
 *    {2'b11, 5'b0_1110}: CAS
 * 4:0 Type[4:0]: Type. This field combined with the Format field specifies the 
 * transaction type. See the encodings in the description for the Fmt[1:0] field. 
 * 
 * ***For the Configuration Request Type, the IRP Protocol Fatal FERR Header 
 * information as below: 
 * 127:96 Addr[63:32]: Upper Address. This field is valid for 64-bit memory request 
 * only. This field should be set to all 0 for 32-bit memory requests, I/O 
 * requests, configuration requests, and completions. 
 * 95:90 Reg[5:0]: Register Number. This field is valid for configuration requests 
 * only. 
 * 83:80 ExtReg[3:0]: Extended Register Number. This field is valid for 
 * configuration requests only. 
 * 79:64 RouteID[15:0]: ID Routing Fields. This field is valid for configuration 
 * requests only. This contains information to route the packet to the target and 
 * is comprised as follows: {device[4:0], function[2:0], bus[7:0]} 
 * 63:60 Last_DW_BE[3:0]: Last DW Byte Enables. This field is valid for memory, 
 * I/O, and configuration requests only. The value in this field is set to all 0 
 * for I/O and configuration requests. 
 * 59:56 1st_DW_BE[3:0]: First DW Byte Enables. This field is valid for memory, I/O 
 * and configuration requests only. 
 * 55:48 Tag[7:0]: Tag. This field is valid for memory, I/O and configuration 
 * requests only. This field in combination with the Requester ID field form a 
 * unique Transaction ID. The value from the original request must be preserved 
 * into the completion. 
 * 47:32 ReqID[15:0]: Requester ID. This field is located here only for memory, 
 * configuration, I/O, and message requests. This field is located elsewhere for 
 * completions. This field in combination with the Tag field form a unique 
 * Transaction ID. The Requester ID is comprised as follows: {device[4:0], 
 * function[2:0], bus[7:0]}. The value from the original request must be preserved 
 * into the completion. 
 * 31:31 TD: TLP Digest. A value of 1 in this field indicates the presence of a 
 * single DW TLP digest at the end of the packet for use in ECRC protection as 
 * defined by the PCIe* specification.  
 * 30:30 EP: Error Poisoned. This field is used to indicate that the data payload 
 * contained in the packet is poisoned.  
 * 29:28 Attr[1:0]: Attributes. These provide hints as to how the packet should be 
 * handled: Bit 1 set to 1 indicates Relaxed Ordering, Bit 0 set to 1 indicates No 
 * Snoop. This field must be set to all 0 for configuration requests, I/O requests, 
 * message requests, and message signaled interrupts.  
 * 27:26 SwRID[6:5]: Switch Routing ID. This field is concatenated with SwRID[4:0] 
 * to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (i.e. 
 * these bit positions are reserved in the PCIe* spec.).This field facilitates 
 * routing of completions through the switch. The upper five bits correspond to the 
 * switch port number assigned to the agent that originated the request and are 
 * used by the switch to route the completion. The lower two bits are provided for 
 * each agent to assign according to its own internal algorithm if needed for 
 * facilitating routing within the agent. The value in this field must be preserved 
 * from the original request requiring a completion and transferred into the 
 * completion. 
 * 25:16 Length[9:0]: Data Length. The data length is specified in DW (4-byte). For 
 * I/O and configuration requests, this field must be set to 1. This field is 
 * reserved for packets that do not contain or refer to data payloads. 
 * 15:15 MAbort: Master Abort Hint. This field is not part of the PCIe* spec. This 
 * field is used by the PCIe/DMI interface block to indicate that the switch 
 * should master abort a request; this would happen if the PCIe* block received an 
 * unsupported request. 
 * 14:12 TC[2:0]: Traffic Class. This allows differentiation of transactions into 
 * eight traffic service classes within the PCIe* interconnect fabric only. For I/O 
 * and configuration requests, this field must be set to all 0. 
 * 11:7 SwRID[4:0]: Switch Routing ID. This field is concatenated with SwRID[6:5] 
 * to form SwRID[6:0]. See description for SwRID[6:5]. 
 * 6:5 Fmt[1:0]: Format. This field combined with the Type field specifies the 
 * transaction type. The encodings for valid {Fmt[1:0], Type[4:0]} combinations:  
 *    {2'b00, 5'b0_0000}: Memory Read  
 *    {2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
 *    {2'b00, 5'b0_0001}: Memory Read  Locked 
 *    {2'b01, 5'b0_0001}: Memory Read with extended address  Locked
 *    {2'b10, 5'b0_0000}: Memory Write 
 *    {2'b11, 5'b0_0000}: Memory Write with extended address 
 *    {2'b00, 5'b0_0010}: I/O Read 
 *    {2'b10, 5'b0_0010}: I/O Write 
 *    {2'b00, 5'b0_0100}: Configuration Read Type 0 
 *    {2'b10, 5'b0_0100}: Configuration Write Type 0 
 *    {2'b00, 5'b0_0101}: Configuration Read Type 1 
 *    {2'b10, 5'b0_0101}: Configuration Write  Type 1 
 *    {2'b00, 5'b1_1011}: Trusted Configuration Read 
 *    {2'b10, 5'b1_1011}: Trusted Configuration Write 
 *    {2'b00, 5'b0_1010}: Completion without Data 
 *    {2'b10, 5'b0_1010}: Completion with Data 
 *    {2'b00, 5'b0_1011}: Completion without Data  Locked 
 *    {2'b10, 5'b0_1011}: Completion with Data  Locked 
 *    {2'b01, 5'b1_0r2r1r0}: Message (r[2:0] are as defined in the PCIe* spec.) 
 *    {2'b11, 5'b1_0r2r1r0}: Message with Data 
 *    {2'b10, 5'b0_1100}: FetchAdd 
 *    {2'b11, 5'b0_1100}: FetchAdd 
 *    {2'b10, 5'b0_1101}: Swap 
 *    {2'b11, 5'b0_1101}: Swap 
 *    {2'b10, 5'b0_1110}: CAS 
 *    {2'b11, 5'b0_1110}: CAS
 * 4:0 Type[4:0]: Type. This field combined with the Format field specifies the 
 * transaction type. See the encodings in the description for the Fmt[1:0] field. 
 * 
 * ***For the Completion Type, the IRP Protocol Fatal FERR Header information as 
 * below: 
 * 127:96 Addr[63:32]: Upper Address. This field is valid for 64-bit memory request 
 * only. This field should be set to all 0 for 32-bit memory requests, I/O 
 * requests, configuration requests, and completions. 
 * 94:88 Lower_Address[6:0]: Lower Address. This field is valid for completions 
 * only. For memory read completions, this is the byte address for the first 
 * enabled byte of data returned. For all other completions, this field is set to 
 * all 0. 
 * 87:80 Tag[7:0]: Tag. This field is valid for completions only. This field in 
 * combination with the Requester ID field form a unique Transaction ID. The value 
 * from the original request must be preserved into the completion. 
 * 79:64 ReqID[15:0]: Requester ID. This field is located here for completions 
 * only. It is located elsewhere for memory, configuration, I/O, and message 
 * requests. This field in combination with the Tag field form a unique Transaction 
 * ID. The Requester ID is comprised as follows: {device[4:0], function[2:0], 
 * bus[7:0]}. The value from the original request must be preserved into the 
 * completion. 
 * 63:56 ByteCnt[7:0]: Byte Count. This field is valid for completions only. For 
 * memory read completions, this specifies the remaining byte count to satisfy the 
 * request including the current packet payload. For all other completions, this 
 * field must be set to 4. This field is concatenated with ByteCnt[11:8] to form 
 * ByteCnt[11:0]. 
 * 55:53 CplStat[2:0]: Completion Status. This field is valid for completions only. 
 * This indicates the status for the completion, encoded as follows:  
 *    3'b000: Successful Completion 
 *    3'b001: Unsupported Request/Master Abort 
 *    3'b010: Configuration Request Retry Status 
 *    3'b100: Completer Abort 
 *    All other encodings are reserved.
 * 52:52 BCM: Byte Count Modified. This field is valid for completions only. This 
 * field is set only in initial completion packets and only by PCI-X completer. A 
 * value of 1 indicates that the Byte Count field reports only the size of the 
 * current packet. 
 * 51:48 ByteCnt[11:8]: Byte Count. This field is valid for completions only. This 
 * field is concatenated with ByteCnt[7:0] to form ByteCnt[11:0]. See description 
 * for ByteCnt[7:0]. 
 * 47:32 CplID[15:0]: Completer ID. This field is valid for completions only. This 
 * uniquely identifies the completer and is comprised as follows: {device[4:0], 
 * function[2:0], bus[7:0]}. 
 * 31:31 TD: TLP Digest. A value of 1 in this field indicates the presence of a 
 * single DW TLP digest at the end of the packet for use in ECRC protection as 
 * defined by the PCIe* specification.  
 * 30:30 EP: Error Poisoned. This field is used to indicate that the data payload 
 * contained in the packet is poisoned.  
 * 29:28 Attr[1:0]: Attributes. These provide hints as to how the packet should be 
 * handled: Bit 1 set to 1 indicates Relaxed Ordering, Bit 0 set to 1 indicates No 
 * Snoop. This field must be set to all 0 for configuration requests, I/O requests, 
 * message requests, and message signaled interrupts. 
 * 27:26 SwRID[6:5]: Switch Routing ID. This field is concatenated with SwRID[4:0] 
 * to form SwRID[6:0]. SwRID[6:0] is not part of the PCIe* specification (i.e. 
 * these bit positions are reserved in the PCIe* spec.).This field facilitates 
 * routing of completions through the switch. The upper five bits correspond to the 
 * switch port number assigned to the agent that originated the request and are 
 * used by the switch to route the completion. The lower two bits are provided for 
 * each agent to assign according to its own internal algorithm if needed for 
 * facilitating routing within the agent. The value in this field must be preserved 
 * from the original request requiring a completion and transferred into the 
 * completion. 
 * 25:16 Length[9:0]: Data Length. The data length is specified in DW (4-byte). For 
 * I/O and configuration requests, this field must be set to 1. This field is 
 * reserved for packets that do not contain or refer to data payloads. 
 * 15:15 MAbort: Master Abort Hint. This field is not part of the PCIe* spec. This 
 * field is used by the PCIe/DMI interface block to indicate that the switch 
 * should master abort a request; this would happen if the PCIe* block received an 
 * unsupported request. 
 * 14:12 TC[2:0]: Traffic Class. This allows differentiation of transactions into 
 * eight traffic service classes within the PCIe* interconnect fabric only. For I/O 
 * and configuration requests, this field must be set to all 0. 
 * 11:7 SwRID[4:0]: Switch Routing ID. This field is concatenated with SwRID[6:5] 
 * to form SwRID[6:0]. See description for SwRID[6:5]. 
 * 6:5 Fmt[1:0]: Format. This field combined with the Type field specifies the 
 * transaction type.                   The encodings for valid {Fmt[1:0], 
 * Type[4:0]} combinations:  
 *    {2'b00, 5'b0_0000}: Memory Read  
 *    {2'b01, 5'b0_0000}: Memory Read with extended (64-bit) address
 *    {2'b00, 5'b0_0001}: Memory Read  Locked 
 *    {2'b01, 5'b0_0001}: Memory Read with extended address  Locked
 *    {2'b10, 5'b0_0000}: Memory Write 
 *    {2'b11, 5'b0_0000}: Memory Write with extended address 
 *    {2'b00, 5'b0_0010}: I/O Read 
 *    {2'b10, 5'b0_0010}: I/O Write 
 *    {2'b00, 5'b0_0100}: Configuration Read Type 0 
 *    {2'b10, 5'b0_0100}: Configuration Write Type 0 
 *    {2'b00, 5'b0_0101}: Configuration Read Type 1 
 *    {2'b10, 5'b0_0101}: Configuration Write  Type 1 
 *    {2'b00, 5'b1_1011}: Trusted Configuration Read 
 *    {2'b10, 5'b1_1011}: Trusted Configuration Write 
 *    {2'b00, 5'b0_1010}: Completion without Data 
 *    {2'b10, 5'b0_1010}: Completion with Data 
 *    {2'b00, 5'b0_1011}: Completion without Data  Locked 
 *    {2'b10, 5'b0_1011}: Completion with Data  Locked 
 *    {2'b01, 5'b1_0r2r1r0}: Message (r[2:0] are as defined in the PCIe* spec.) 
 *    {2'b11, 5'b1_0r2r1r0}: Message with Data 
 *    {2'b10, 5'b0_1100}: FetchAdd 
 *    {2'b11, 5'b0_1100}: FetchAdd 
 *    {2'b10, 5'b0_1101}: Swap 
 *    {2'b11, 5'b0_1101}: Swap 
 *    {2'b10, 5'b0_1110}: CAS 
 *    {2'b11, 5'b0_1110}: CAS
 * 4:0 Type[4:0]: Type. This field combined with the Format field specifies the 
 * transaction type. See the encodings in the description for the Fmt[1:0] field. 
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the first DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP1FFERRHD0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1FFERRHD1_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A2C4)                                                  */
/*       IVT_EX (0x4002A2C4)                                                  */
/*       HSX (0x4002A2C4)                                                     */
/*       BDX (0x4002A2C4)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1FFERRHD1_IIO_RAS_REG 0x090242C4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Header Log 1.
 * Refer to IRPPxFFERRHD0 for details.
 * 
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the second DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP1FFERRHD1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1FFERRHD2_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A2C8)                                                  */
/*       IVT_EX (0x4002A2C8)                                                  */
/*       HSX (0x4002A2C8)                                                     */
/*       BDX (0x4002A2C8)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1FFERRHD2_IIO_RAS_REG 0x090242C8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Header Log 2.
 * Refer to IRPPxFFERRHD0 for details.
 * 
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the third DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP1FFERRHD2_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1FFERRHD3_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A2CC)                                                  */
/*       IVT_EX (0x4002A2CC)                                                  */
/*       HSX (0x4002A2CC)                                                     */
/*       BDX (0x4002A2CC)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1FFERRHD3_IIO_RAS_REG 0x090242CC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Fatal FERR Header Log 3.
 * Refer to IRPPxFFERRHD0 for details.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the fourth DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP1FFERRHD3_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1NFERRST_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A2D0)                                                  */
/*       IVT_EX (0x4002A2D0)                                                  */
/*       HSX (0x4002A2D0)                                                     */
/*       BDX (0x4002A2D0)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1NFERRST_IIO_RAS_REG 0x090242D0


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal First Error.
 * The error status log indicates which error is causing the report of the first 
 * non-fatal error event. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
       
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1NFERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal First Error.
 * The error status log indicates which error is causing the report of the first 
 * non-fatal error event. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
       
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1NFERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP1NNERRST_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A2D4)                                                  */
/*       IVT_EX (0x4002A2D4)                                                  */
/*       HSX (0x4002A2D4)                                                     */
/*       BDX (0x4002A2D4)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1NNERRST_IIO_RAS_REG 0x090242D4


#if defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal NERR Status.
 * The error status log indicates which error is causing the report of the next 
 * non-fatal error event (any event that is not the first). 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 rsvd_15 : 17;
    /* rsvd_15 - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1NNERRST_IIO_RAS_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) */

#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal NERR Status.
 * The error status log indicates which error is causing the report of the next 
 * non-fatal error event (any event that is not the first). 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 wrcache_correcc_error_cs0 : 1;
    /* wrcache_correcc_error_cs0 - Bits[1:1], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set0. 
     */
    UINT32 wrcache_correcc_error_cs1 : 1;
    /* wrcache_correcc_error_cs1 - Bits[2:2], ROS_V, default = 1'b0 
       (Error Code 0xB4)
       A single bit ECC error was detected and corrected within the Write Cache in 
       set1. 
     */
    UINT32 protocol_rcvd_poison : 1;
    /* protocol_rcvd_poison - Bits[3:3], ROS_V, default = 1'b0 
       (Error Code 0xC1)
       A poisoned packet has been received from the Coherent Interface.
     */
    UINT32 wrcache_uncecc_error_cs0 : 1;
    /* wrcache_uncecc_error_cs0 - Bits[4:4], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set0.
     */
    UINT32 wrcache_uncecc_error_cs1 : 1;
    /* wrcache_uncecc_error_cs1 - Bits[5:5], ROS_V, default = 1'b0 
       (Error Code 0xC2)
       A double bit ECC error was detected within the Write Cache in set1.
     */
    UINT32 csr_acc_32b_unaligned : 1;
    /* csr_acc_32b_unaligned - Bits[6:6], ROS_V, default = 1'b0 
       (Error Code 0xC3)
       CSR access crossing 32-bit boundary.
     */
    UINT32 rsvd_7 : 3;
    /* rsvd_7 - Bits[9:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_rcvd_unexprsp : 1;
    /* protocol_rcvd_unexprsp - Bits[10:10], ROS_V, default = 1'b0 
       (Error Code 0xD7)
       A completion has been received from the Coherent Interface that was unexpected.
     */
    UINT32 rsvd_11 : 2;
    /* rsvd_11 - Bits[12:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 protocol_qt_overflow_underflow : 1;
    /* protocol_qt_overflow_underflow - Bits[13:13], ROS_V, default = 1'b0 
       (Error Code 0xDA)
       Protocol Queue/Table Overflow or Underflow.
     */
    UINT32 protocol_parity_error : 1;
    /* protocol_parity_error - Bits[14:14], ROS_V, default = 1'b0 
       (Error Code 0xDB)
       Logs parity errors on data from the IIO switch on the inbound path.
     */
    UINT32 irp2sw_path_parity_error : 1;
    /* irp2sw_path_parity_error - Bits[15:15], RW1CS, default = 1'b0 
       logs parity errors on irp cache to switch data path in the irp
     */
    UINT32 ring2cache_64bit_ncs_path_parity_error : 1;
    /* ring2cache_64bit_ncs_path_parity_error - Bits[16:16], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache ncs data path in the irp
     */
    UINT32 ring2cache_path_parity_error : 1;
    /* ring2cache_path_parity_error - Bits[17:17], RW1CS, default = 1'b0 
       logs parity errors on r2 to the cache data path in the irp
     */
    UINT32 ring2cache_ncb_path_parity_error : 1;
    /* ring2cache_ncb_path_parity_error - Bits[18:18], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncb data path in the irp
     */
    UINT32 ring2cache_ncs_path_parity_error : 1;
    /* ring2cache_ncs_path_parity_error - Bits[19:19], RW1CS, default = 1'b0 
       logs parity errors on ring to irp ncs data path in the irp0.
     */
    UINT32 rsvd_20 : 12;
    /* rsvd_20 - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1NNERRST_IIO_RAS_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */



/* IRPP1NFERRHD0_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A2D8)                                                  */
/*       IVT_EX (0x4002A2D8)                                                  */
/*       HSX (0x4002A2D8)                                                     */
/*       BDX (0x4002A2D8)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1NFERRHD0_IIO_RAS_REG 0x090242D8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal FERR Header Log 0.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the first DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP1NFERRHD0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1NFERRHD1_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A2DC)                                                  */
/*       IVT_EX (0x4002A2DC)                                                  */
/*       HSX (0x4002A2DC)                                                     */
/*       BDX (0x4002A2DC)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1NFERRHD1_IIO_RAS_REG 0x090242DC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal FERR Header Log 1.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the second DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP1NFERRHD1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1NFERRHD2_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A2E0)                                                  */
/*       IVT_EX (0x4002A2E0)                                                  */
/*       HSX (0x4002A2E0)                                                     */
/*       BDX (0x4002A2E0)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1NFERRHD2_IIO_RAS_REG 0x090242E0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal FERR Header Log 2.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the third DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP1NFERRHD2_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1NFERRHD3_IIO_RAS_REG supported on:                                    */
/*       IVT_EP (0x4002A2E4)                                                  */
/*       IVT_EX (0x4002A2E4)                                                  */
/*       HSX (0x4002A2E4)                                                     */
/*       BDX (0x4002A2E4)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1NFERRHD3_IIO_RAS_REG 0x090242E4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Non-Fatal FERR Header Log 3.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Logs the fourth DWORD of the header on an error condition
     */
  } Bits;
  UINT32 Data;
} IRPP1NFERRHD3_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1ERRCNTSEL_IIO_RAS_REG supported on:                                   */
/*       IVT_EP (0x4002A2E8)                                                  */
/*       IVT_EX (0x4002A2E8)                                                  */
/*       HSX (0x4002A2E8)                                                     */
/*       BDX (0x4002A2E8)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1ERRCNTSEL_IIO_RAS_REG 0x090242E8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Counter Select.
 */
typedef union {
  struct {
    UINT32 irp_error_count_select : 19;
    /* irp_error_count_select - Bits[18:0], RW, default = 19'b0000000000000000000 
       See IRPP0ERRST for per bit description of each error. Each bit in this field has 
       the following behavior: 
       0: Do not select this error type for error counting
       1: Select this error type for error counting
     */
    UINT32 rsvd : 13;
    /* rsvd - Bits[31:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1ERRCNTSEL_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IRPP1ERRCNT_IIO_RAS_REG supported on:                                      */
/*       IVT_EP (0x4002A2EC)                                                  */
/*       IVT_EX (0x4002A2EC)                                                  */
/*       HSX (0x4002A2EC)                                                     */
/*       BDX (0x4002A2EC)                                                     */
/* Register default value:              0x00000000                            */
#define IRPP1ERRCNT_IIO_RAS_REG 0x090242EC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IRP Protocol Error Count.
 */
typedef union {
  struct {
    UINT32 errcnt : 7;
    /* errcnt - Bits[6:0], RW1CS, default = 7'b0000000 
       This counter accumulates errors that occur when the associated error type is 
       selected in the ERRCNTSEL register. 
       
       Notes:
       This register is cleared by writing 7Fh.
       Maximum counter available is 127d (7Fh)
     */
    UINT32 errovf : 1;
    /* errovf - Bits[7:7], RW1CS, default = 1'b0 
       Error Accumulator Overflow
       0: No overflow occurred
       1: Error overflow. The error count may not be valid.
     */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IRPP1ERRCNT_IIO_RAS_STRUCT;
#endif /* ASM_INC */








/* IIOERRST_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A300)                                                  */
/*       IVT_EX (0x4002A300)                                                  */
/*       HSX (0x4002A300)                                                     */
/*       BDX (0x4002A300)                                                     */
/* Register default value:              0x00000000                            */
#define IIOERRST_IIO_RAS_REG 0x09024300


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IIO Core Error Status.
 * This register indicates the IIO internal core errors detected by the IIO error 
 * logic. An individual error status bit that is set indicates that a particular 
 * error occurred; software may clear an error status by writing a 1 to the 
 * respective bit. This register is sticky and can only be reset by PWRGOOD. 
 * Clearing of the IIO**ERRST is done by clearing the corresponding IIOERRST bits.  
 */
typedef union {
  struct {
    UINT32 c7_multicast_target_error : 1;
    /* c7_multicast_target_error - Bits[0:0], RW1CS, default = 1'b0 
       Multicast target error indicating a multicast transaction has targeted more than 
       the number of groups supported. 
     */
    UINT32 rsvd_1 : 3;
    UINT32 c4 : 1;
    /* c4 - Bits[4:4], RW1CS, default = 1'b0 
       Master Abort Error Status (C4)
     */
    UINT32 c5 : 1;
    /* c5 - Bits[5:5], RW1CS, default = 1'b0 
       Completer Abort Error Status (C5)
     */
    UINT32 c6 : 1;
    /* c6 - Bits[6:6], RW1CS, default = 1'b0 
       Overflow/Underflow Error Status (C6)
     */
    UINT32 reserved : 25;
    /* reserved - Bits[31:7], RO, default = 25'b0000000000000000000000000 
       1
     */
  } Bits;
  UINT32 Data;
} IIOERRST_IIO_RAS_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* IIOERRCTL_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A304)                                                  */
/*       IVT_EX (0x4002A304)                                                  */
/*       HSX (0x4002A304)                                                     */
/*       BDX (0x4002A304)                                                     */
/* Register default value on IVT_EP:    0x00000000                            */
/* Register default value on IVT_EX:    0x00000000                            */
/* Register default value on HSX:       0x00000400                            */
/* Register default value on BDX:       0x00000400                            */
#define IIOERRCTL_IIO_RAS_REG 0x09024304


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IIO Core Error Control.
 * This register controls the reporting of IIO internal core errors detected by the 
 * IIO error logic. An individual error control bit that is cleared masks reporting 
 * of that a particular error; software may set or clear the respective bit. This 
 * register is sticky and can only be reset by PWRGOOD. 
 */
typedef union {
  struct {
    UINT32 c7_multicast_target_error : 1;
    /* c7_multicast_target_error - Bits[0:0], RWS_L, default = 1'b0 
       Multicast Target Error Enable.
     */
    UINT32 rsvd_1 : 3;
    UINT32 c4 : 1;
    /* c4 - Bits[4:4], RWS_L, default = 1'b0 
       Master Abort Error Enable (C4)
     */
    UINT32 c5 : 1;
    /* c5 - Bits[5:5], RWS_L, default = 1'b0 
       Completer Abort Error Enable (C5)
     */
    UINT32 c6 : 1;
    /* c6 - Bits[6:6], RWS_L, default = 1'b0 
       Overflow/Underflow Error Enable (C6)
     */
    UINT32 c4_outbound_ler_disable : 1;
    /* c4_outbound_ler_disable - Bits[7:7], RWS_L, default = 1'b0 
       Disables logging C4 error due to the PCIE port being down due to being in LER 
       mode when set to one. 
     */
    UINT32 c4_inbound_ler_disable : 1;
    /* c4_inbound_ler_disable - Bits[8:8], RWS_L, default = 1'b0 
       Disables logging C4 error due to the PCIE port being down due to being in LER 
       mode when set to one. 
     */
    UINT32 c4_viral_disable : 1;
    /* c4_viral_disable - Bits[9:9], RWS_L, default = 1'b0 
       Disables logging C4 error and PCIE UR in VIRAL state when set to one.
       Disabling C4 error logging is dependent on viral state being asserted not viral 
       status. It is recommended that traffic towards the IIO be quiesced before 
       clearing the viral state to avoid a race condition between clearing the register 
       bit and the IIO exiting Viral. 
     */
    UINT32 c8_ib_header_parity_detect : 1;
    /* c8_ib_header_parity_detect - Bits[10:10], RWS_L, default = 1'b1 
       Enables detection of inbound header FIFO parity errors at the FIFO output 
       (heavier disable than the enable bit below). 
     */
    UINT32 c8_ib_header_parity_core_poison_en : 1;
    /* c8_ib_header_parity_core_poison_en - Bits[11:11], RWS_L, default = 1'b0 
       On detecting a header parity error on a write or completion with data that is 
       targeting a core or remote PCIe device, poison it. 
     */
    UINT32 c8_ib_header_parity_p2p_poison_en : 1;
    /* c8_ib_header_parity_p2p_poison_en - Bits[12:12], RWS_L, default = 1'b0 
       On detecting a header parity error on a write or completion with data that is 
       targeting a local PCIe device, poison it. 
     */
    UINT32 c8_ib_header_parity_sticky_poison : 1;
    /* c8_ib_header_parity_sticky_poison - Bits[13:13], RWS_L, default = 1'b0 
       Once an inbound header parity error is detected, poison all subsequent 
       completions. 
     */
    UINT32 rsvd : 18;
    /* rsvd - Bits[31:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIOERRCTL_IIO_RAS_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* IIOFFERRST_IIO_RAS_REG supported on:                                       */
/*       IVT_EP (0x4002A308)                                                  */
/*       IVT_EX (0x4002A308)                                                  */
/*       HSX (0x4002A308)                                                     */
/*       BDX (0x4002A308)                                                     */
/* Register default value:              0x00000000                            */
#define IIOFFERRST_IIO_RAS_REG 0x09024308
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Fatal FERR Status.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_status_log : 7;
    /* ioh_core_error_status_log - Bits[6:0], ROS_V, default = 7'b0000000 
       The error status log indicates which error is causing the report of the first 
       error event. The encoding indicates the corresponding bit position of the error 
       in the error status register. 
       It has the same field mapping as IIOERRST.
     */
    UINT32 rsvd : 25;
    /* rsvd - Bits[31:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIOFFERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIOFFERRHD_0_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A30C)                                                  */
/*       IVT_EX (0x4002A30C)                                                  */
/*       HSX (0x4002A30C)                                                     */
/*       BDX (0x4002A30C)                                                     */
/* Register default value:              0x00000000                            */
#define IIOFFERRHD_0_IIO_RAS_REG 0x0902430C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Fatal FERR Header 0.
 * Header log stores the IIO data path header information of the associated IIO 
 * core error. The header indicates where the error is originating from and the 
 * address of the cycle. 
 * The IIO Core Fatal FERR Header has 128 bits comprised of iiofferrhd_[3-0] 
 * registers as follows. 
 * 127:90	Reserved.
 * 89:89	Error Type: 0: MA, 1: CA
 * 88:81	Message Code.
 * 80:65	MSI Data. 
 * 64:58	Internal Routing ID. 
 * 57:56	Fmt.
 * 55:51	Type. 
 * 50:0	Address.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_header_log : 32;
    /* ioh_core_error_header_log - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bits 31:0 of iiofferrhd[127:0].
     */
  } Bits;
  UINT32 Data;
} IIOFFERRHD_0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIOFFERRHD_1_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A310)                                                  */
/*       IVT_EX (0x4002A310)                                                  */
/*       HSX (0x4002A310)                                                     */
/*       BDX (0x4002A310)                                                     */
/* Register default value:              0x00000000                            */
#define IIOFFERRHD_1_IIO_RAS_REG 0x09024310
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Fatal FERR Header 1.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_header_log : 32;
    /* ioh_core_error_header_log - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bits 63:32 of iiofferrhd[127:0].
     */
  } Bits;
  UINT32 Data;
} IIOFFERRHD_1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIOFFERRHD_2_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A314)                                                  */
/*       IVT_EX (0x4002A314)                                                  */
/*       HSX (0x4002A314)                                                     */
/*       BDX (0x4002A314)                                                     */
/* Register default value:              0x00000000                            */
#define IIOFFERRHD_2_IIO_RAS_REG 0x09024314
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Fatal FERR Header 2.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_header_log : 32;
    /* ioh_core_error_header_log - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bits 95:64 of iiofferrhd[127:0].
     */
  } Bits;
  UINT32 Data;
} IIOFFERRHD_2_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIOFFERRHD_3_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A318)                                                  */
/*       IVT_EX (0x4002A318)                                                  */
/*       HSX (0x4002A318)                                                     */
/*       BDX (0x4002A318)                                                     */
/* Register default value:              0x00000000                            */
#define IIOFFERRHD_3_IIO_RAS_REG 0x09024318
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Fatal FERR Header 3.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_header_log : 32;
    /* ioh_core_error_header_log - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bits 127:96 of iiofferrhd[127:0].
     */
  } Bits;
  UINT32 Data;
} IIOFFERRHD_3_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIOFNERRST_IIO_RAS_REG supported on:                                       */
/*       IVT_EP (0x4002A31C)                                                  */
/*       IVT_EX (0x4002A31C)                                                  */
/*       HSX (0x4002A31C)                                                     */
/*       BDX (0x4002A31C)                                                     */
/* Register default value:              0x00000000                            */
#define IIOFNERRST_IIO_RAS_REG 0x0902431C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Non-Fatal FERR Status.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_status_log : 7;
    /* ioh_core_error_status_log - Bits[6:0], ROS_V, default = 7'b0000000 
       The error status log indicates which error is causing the report of the first 
       error event. The encoding indicates the corresponding bit position of the error 
       in the error status register. 
       It has the same field mapping as IIOERRST.
     */
    UINT32 rsvd : 25;
    /* rsvd - Bits[31:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIOFNERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIONFERRST_IIO_RAS_REG supported on:                                       */
/*       IVT_EP (0x4002A320)                                                  */
/*       IVT_EX (0x4002A320)                                                  */
/*       HSX (0x4002A320)                                                     */
/*       BDX (0x4002A320)                                                     */
/* Register default value:              0x00000000                            */
#define IIONFERRST_IIO_RAS_REG 0x09024320
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Non-Fatal FERR Status.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_status_log : 7;
    /* ioh_core_error_status_log - Bits[6:0], ROS_V, default = 7'b0000000 
       The error status log indicates which error is causing the report of the first 
       error event. The encoding indicates the corresponding bit position of the error 
       in the error status register. 
       It has the same field mapping as IIOERRST.
     */
    UINT32 rsvd : 25;
    /* rsvd - Bits[31:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIONFERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIONFERRHD_0_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A324)                                                  */
/*       IVT_EX (0x4002A324)                                                  */
/*       HSX (0x4002A324)                                                     */
/*       BDX (0x4002A324)                                                     */
/* Register default value:              0x00000000                            */
#define IIONFERRHD_0_IIO_RAS_REG 0x09024324
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Non-Fatal FERR Header 0.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_header_log : 32;
    /* ioh_core_error_header_log - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bits 31:0 of iionferrhd[127:0]
     */
  } Bits;
  UINT32 Data;
} IIONFERRHD_0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIONFERRHD_1_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A328)                                                  */
/*       IVT_EX (0x4002A328)                                                  */
/*       HSX (0x4002A328)                                                     */
/*       BDX (0x4002A328)                                                     */
/* Register default value:              0x00000000                            */
#define IIONFERRHD_1_IIO_RAS_REG 0x09024328
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Non-Fatal FERR Header 1.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_header_log : 32;
    /* ioh_core_error_header_log - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bits 63:32 of iionferrhd[127:0].
     */
  } Bits;
  UINT32 Data;
} IIONFERRHD_1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIONFERRHD_2_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A32C)                                                  */
/*       IVT_EX (0x4002A32C)                                                  */
/*       HSX (0x4002A32C)                                                     */
/*       BDX (0x4002A32C)                                                     */
/* Register default value:              0x00000000                            */
#define IIONFERRHD_2_IIO_RAS_REG 0x0902432C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Non-Fatal FERR Header 2.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_header_log : 32;
    /* ioh_core_error_header_log - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bits 95:64 of iionferrhd[127:0].
     */
  } Bits;
  UINT32 Data;
} IIONFERRHD_2_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIONFERRHD_3_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A330)                                                  */
/*       IVT_EX (0x4002A330)                                                  */
/*       HSX (0x4002A330)                                                     */
/*       BDX (0x4002A330)                                                     */
/* Register default value:              0x00000000                            */
#define IIONFERRHD_3_IIO_RAS_REG 0x09024330
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Non-Fatal FERR Header 3.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_header_log : 32;
    /* ioh_core_error_header_log - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bits 127:96 of iionferrhd[127:0].
     */
  } Bits;
  UINT32 Data;
} IIONFERRHD_3_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIONNERRST_IIO_RAS_REG supported on:                                       */
/*       IVT_EP (0x4002A334)                                                  */
/*       IVT_EX (0x4002A334)                                                  */
/*       HSX (0x4002A334)                                                     */
/*       BDX (0x4002A334)                                                     */
/* Register default value:              0x00000000                            */
#define IIONNERRST_IIO_RAS_REG 0x09024334
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Non-Fatal NERR Status.
 */
typedef union {
  struct {
    UINT32 ioh_core_error_status_log : 7;
    /* ioh_core_error_status_log - Bits[6:0], ROS_V, default = 7'b0000000 
       The error status log indicates which error is causing the report of the first 
       error event. The encoding indicates the corresponding bit position of the error 
       in the error status register. 
       It has the same field mapping as IIOERRST.
     */
    UINT32 rsvd : 25;
    /* rsvd - Bits[31:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIONNERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* IIOERRCNTSEL_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A33C)                                                  */
/*       IVT_EX (0x4002A33C)                                                  */
/*       HSX (0x4002A33C)                                                     */
/*       BDX (0x4002A33C)                                                     */
/* Register default value:              0x00000000                            */
#define IIOERRCNTSEL_IIO_RAS_REG 0x0902433C


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.2.CFG.xml.
 * IIO Core Error Counter Selection.
 */
typedef union {
  struct {
    UINT32 c7_multicast_target_error : 1;
    /* c7_multicast_target_error - Bits[0:0], RW_L, default = 1'b0 
       Multicast Target Error Select
     */
    UINT32 c8_ib_header_parity : 1;
    /* c8_ib_header_parity - Bits[1:1], RW_L, default = 1'b0 
       1
     */
    UINT32 twofive_core_header_queue_parity_error_select : 1;
    /* twofive_core_header_queue_parity_error_select - Bits[2:2], RW_L, default = 1'b0 
       1
     */
    UINT32 thirteen_msi_address_error_select : 1;
    /* thirteen_msi_address_error_select - Bits[3:3], RW_L, default = 1'b0 
       1
     */
    UINT32 c4 : 1;
    /* c4 - Bits[4:4], RW_L, default = 1'b0 
       Master Abort Error Select
     */
    UINT32 c5 : 1;
    /* c5 - Bits[5:5], RW_L, default = 1'b0 
       Completer Abort Error Select
     */
    UINT32 c6 : 1;
    /* c6 - Bits[6:6], RW_L, default = 1'b0 
       Overflow/Underflow Error Count Select
     */
    UINT32 rsvd : 25;
    /* rsvd - Bits[31:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIOERRCNTSEL_IIO_RAS_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* IIOERRCNT_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A340)                                                  */
/*       IVT_EX (0x4002A340)                                                  */
/*       HSX (0x4002A340)                                                     */
/*       BDX (0x4002A340)                                                     */
/* Register default value:              0x00000000                            */
#define IIOERRCNT_IIO_RAS_REG 0x09024340
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * IIO Core Error Counter.
 */
typedef union {
  struct {
    UINT32 errcnt : 7;
    /* errcnt - Bits[6:0], RW1CS, default = 7'b0000000 
       This counter accumulates errors that occur when the associated error type is 
       selected in the ERRCNTSEL register. 
       
       Notes:
       This register is cleared by writing 7Fh.
       Maximum counter available is 127d (7Fh).
     */
    UINT32 errovf : 1;
    /* errovf - Bits[7:7], RW1CS, default = 1'b0 
       0: No overflow occurred
       1: Error overflow. The error count may not be valid.
     */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IIOERRCNT_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIERRST_IIO_RAS_REG supported on:                                          */
/*       IVT_EP (0x4002A380)                                                  */
/*       IVT_EX (0x4002A380)                                                  */
/*       HSX (0x4002A380)                                                     */
/*       BDX (0x4002A380)                                                     */
/* Register default value:              0x00000000                            */
#define MIERRST_IIO_RAS_REG 0x09024380
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Error Status.
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 3;
    UINT32 vpp_err_sts : 1;
    /* vpp_err_sts - Bits[3:3], RW1CS, default = 1'b0 
       VPP Hotplug I/O Extender Port Error Status. I/O module encountered persistent 
       VPP failure. The VPP is unable to operate. 
     */
    UINT32 rsvd_4 : 1;
    UINT32 rsvd : 27;
    /* rsvd - Bits[31:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MIERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIERRCTL_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x4002A384)                                                  */
/*       IVT_EX (0x4002A384)                                                  */
/*       HSX (0x4002A384)                                                     */
/*       BDX (0x4002A384)                                                     */
/* Register default value:              0x00000000                            */
#define MIERRCTL_IIO_RAS_REG 0x09024384
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Error Control.
 */
typedef union {
  struct {
    UINT32 cfg_reg_par : 1;
    /* cfg_reg_par - Bits[0:0], RWS, default = 1'b0 
       Config Register Parity Error Enable
     */
    UINT32 smbus_port_sts : 1;
    /* smbus_port_sts - Bits[1:1], RWS, default = 1'b0 
       This bit has no effect.
     */
    UINT32 jtag_tap_sts : 1;
    /* jtag_tap_sts - Bits[2:2], RWS, default = 1'b0 
       JTAG TAP Status Enable
     */
    UINT32 vpp_err_sts : 1;
    /* vpp_err_sts - Bits[3:3], RWS, default = 1'b0 
       VPP Error Status Enable.
     */
    UINT32 dfx_inj_err : 1;
    /* dfx_inj_err - Bits[4:4], RWS, default = 1'b0 
       DFx Injection Error Enable
     */
    UINT32 rsvd : 27;
    /* rsvd - Bits[31:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MIERRCTL_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIFFERRST_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A388)                                                  */
/*       IVT_EX (0x4002A388)                                                  */
/*       HSX (0x4002A388)                                                     */
/*       BDX (0x4002A388)                                                     */
/* Register default value:              0x00000000                            */
#define MIFFERRST_IIO_RAS_REG 0x09024388
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Status.
 */
typedef union {
  struct {
    UINT32 mi_err_st_log : 11;
    /* mi_err_st_log - Bits[10:0], ROS_V, default = 11'b00000000000 
       There is 1 bit per VPP port to support up to 11 slots. This field only logs VPP 
       errors. Vpp is serial bus that indicates which port (slot) has a hot plug event 
       pending. 
     */
    UINT32 rsvd : 21;
    /* rsvd - Bits[31:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MIFFERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIFFERRHDR_0_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A38C)                                                  */
/*       IVT_EX (0x4002A38C)                                                  */
/*       HSX (0x4002A38C)                                                     */
/*       BDX (0x4002A38C)                                                     */
/* Register default value:              0x00000000                            */
#define MIFFERRHDR_0_IIO_RAS_REG 0x0902438C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Header Log 0. 
 * The header totally has 128 bits comprised of mifferrhdr_[0-3] as described as 
 * follows. 
 * 127:96	Reserved.
 * 95:95 vpp_reset_mode:
 * 0: Power good reset will reset the VPP state machines and hard reset will cause 
 * the VPP state machine to terminate at the next logical VPP stream boundary and 
 * then reset the VPP state machines 
 * 1: Both power good and hard reset will reset the VPP state machines 
 * 94:87 vpp_en: When set, the VPP function for the corresponding root port is 
 * enabled.  
 * Enable Root Port
 * [39] reserved.
 * [38] reserved.
 * [37] reserved.
 * [36] reserved.
 * [35] Memory Channel 3
 * [34] Memory Channel 2
 * [33] Memory Channel 1
 * [32] Memory Channel 0
 * 86:55 vpp_enaddr: Assigns the VPP address of the device on the VPP interface and 
 * assigns the port address for the ports within the VPP device. There are for 
 * memory channel hotplug. 
 * Port Addr Root Port
 * [31] [30:28] Reserved
 * [27] [27:24] Reserved
 * [23] [22:20] Reserved
 * [19] [18:16] Reserved
 * [15] [14:12] Memory Channel 3
 * [11] [10:8] Memory Channel 2
 * [7] [6:4] Memory Channel 1
 * [3] [2:0] Memory Channel 0
 * 54:44 vpp_en: When set, the VPP function for the corresponding root port is 
 * enabled. 
 * Enable Root Port
 * [54] Port 3d
 * [53] Port 3c
 * [52] Port 3b
 * [51] Port 3a
 * [50] Port 2d
 * [49] Port 2c
 * [48] Port 2b
 * [47] Port 2a
 * [46] Port 1b
 * [45] Port 1a
 * [44] Port 0 (PCIe* mode only) 
 * 43:0 vpp_enaddr: Assigns the VPP address of the device on the VPP interface and 
 * assigns the port address for the ports within the VPP device. There are more 
 * address bits then root ports so assignment must be spread across VPP ports. 
 * Port Addr Root Port
 * [43] [42:40] Port 3d
 * [39] [38:36] Port 3c
 * [35] [34:32] Port 3b
 * [31] [30:28] Port 3a
 * [27] [27:24] Port 2d
 * [23] [22:20] Port 2c
 * [19] [18:16] Port 2b
 * [15] [14:12] Port 2a
 * [11] [10:8] Port 1b
 * [7] [6:4] Port 1a
 * [3] [2:0] Port 0 (PCIe* mode only)
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bit 31:0 of header log.
     */
  } Bits;
  UINT32 Data;
} MIFFERRHDR_0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIFFERRHDR_1_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A390)                                                  */
/*       IVT_EX (0x4002A390)                                                  */
/*       HSX (0x4002A390)                                                     */
/*       BDX (0x4002A390)                                                     */
/* Register default value:              0x00000000                            */
#define MIFFERRHDR_1_IIO_RAS_REG 0x09024390
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Header Log 1.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bit 63:32 of header log.
     */
  } Bits;
  UINT32 Data;
} MIFFERRHDR_1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIFFERRHDR_2_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A394)                                                  */
/*       IVT_EX (0x4002A394)                                                  */
/*       HSX (0x4002A394)                                                     */
/*       BDX (0x4002A394)                                                     */
/* Register default value:              0x00000000                            */
#define MIFFERRHDR_2_IIO_RAS_REG 0x09024394
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Header Log 2.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bit 95:64 of header log.
     */
  } Bits;
  UINT32 Data;
} MIFFERRHDR_2_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIFFERRHDR_3_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A398)                                                  */
/*       IVT_EX (0x4002A398)                                                  */
/*       HSX (0x4002A398)                                                     */
/*       BDX (0x4002A398)                                                     */
/* Register default value:              0x00000000                            */
#define MIFFERRHDR_3_IIO_RAS_REG 0x09024398
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Header Log 3.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bit 127:96 of header log.
     */
  } Bits;
  UINT32 Data;
} MIFFERRHDR_3_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIFNERRST_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A39C)                                                  */
/*       IVT_EX (0x4002A39C)                                                  */
/*       HSX (0x4002A39C)                                                     */
/*       BDX (0x4002A39C)                                                     */
/* Register default value:              0x00000000                            */
#define MIFNERRST_IIO_RAS_REG 0x0902439C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal NERR Status.
 */
typedef union {
  struct {
    UINT32 mi_err_st_log : 11;
    /* mi_err_st_log - Bits[10:0], ROS_V, default = 11'b00000000000 
       There is 1 bit per VPP port to support up to 11 slots. This field only logs VPP 
       errors. Vpp is serial bus that indicates which port (slot) has a hot plug event 
       pending. 
     */
    UINT32 rsvd : 21;
    /* rsvd - Bits[31:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MIFNERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MINFERRST_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A3A0)                                                  */
/*       IVT_EX (0x4002A3A0)                                                  */
/*       HSX (0x4002A3A0)                                                     */
/*       BDX (0x4002A3A0)                                                     */
/* Register default value:              0x00000000                            */
#define MINFERRST_IIO_RAS_REG 0x090243A0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Non-Fatal FERR Status.
 */
typedef union {
  struct {
    UINT32 mi_err_st_log : 11;
    /* mi_err_st_log - Bits[10:0], ROS_V, default = 11'b00000000000 
       There is 1 bit per VPP port to support up to 11 slots. This field only logs VPP 
       errors. Vpp is serial bus that indicates which port (slot) has a hot plug event 
       pending. 
     */
    UINT32 rsvd : 21;
    /* rsvd - Bits[31:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MINFERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MINFERRHDR_0_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A3A4)                                                  */
/*       IVT_EX (0x4002A3A4)                                                  */
/*       HSX (0x4002A3A4)                                                     */
/*       BDX (0x4002A3A4)                                                     */
/* Register default value:              0x00000000                            */
#define MINFERRHDR_0_IIO_RAS_REG 0x090243A4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Header Log 0.
 * Refer to mifferrhdr_0 for decoding.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bit 31:0 of header log.
     */
  } Bits;
  UINT32 Data;
} MINFERRHDR_0_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MINFERRHDR_1_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A3A8)                                                  */
/*       IVT_EX (0x4002A3A8)                                                  */
/*       HSX (0x4002A3A8)                                                     */
/*       BDX (0x4002A3A8)                                                     */
/* Register default value:              0x00000000                            */
#define MINFERRHDR_1_IIO_RAS_REG 0x090243A8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Header Log 1.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bit 63:32 of header log.
     */
  } Bits;
  UINT32 Data;
} MINFERRHDR_1_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MINFERRHDR_2_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A3AC)                                                  */
/*       IVT_EX (0x4002A3AC)                                                  */
/*       HSX (0x4002A3AC)                                                     */
/*       BDX (0x4002A3AC)                                                     */
/* Register default value:              0x00000000                            */
#define MINFERRHDR_2_IIO_RAS_REG 0x090243AC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Header Log 2.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bit 95:64 of header log.
     */
  } Bits;
  UINT32 Data;
} MINFERRHDR_2_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MINFERRHDR_3_IIO_RAS_REG supported on:                                     */
/*       IVT_EP (0x4002A3B0)                                                  */
/*       IVT_EX (0x4002A3B0)                                                  */
/*       HSX (0x4002A3B0)                                                     */
/*       BDX (0x4002A3B0)                                                     */
/* Register default value:              0x00000000                            */
#define MINFERRHDR_3_IIO_RAS_REG 0x090243B0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Fatal FERR Header Log 3.
 */
typedef union {
  struct {
    UINT32 hdr : 32;
    /* hdr - Bits[31:0], ROS_V, default = 32'b00000000000000000000000000000000 
       Bit 127:96 of header log.
     */
  } Bits;
  UINT32 Data;
} MINFERRHDR_3_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MINNERRST_IIO_RAS_REG supported on:                                        */
/*       IVT_EP (0x4002A3B4)                                                  */
/*       IVT_EX (0x4002A3B4)                                                  */
/*       HSX (0x4002A3B4)                                                     */
/*       BDX (0x4002A3B4)                                                     */
/* Register default value:              0x00000000                            */
#define MINNERRST_IIO_RAS_REG 0x090243B4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Non-Fatal NERR Status.
 */
typedef union {
  struct {
    UINT32 mi_err_st_log : 11;
    /* mi_err_st_log - Bits[10:0], ROS_V, default = 11'b00000000000 
       There is 1 bit per VPP port to support up to 11 slots. This field only logs VPP 
       errors. Vpp is serial bus that indicates which port (slot) has a hot plug event 
       pending. 
     */
    UINT32 rsvd : 21;
    /* rsvd - Bits[31:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MINNERRST_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIERRCNTSEL_IIO_RAS_REG supported on:                                      */
/*       IVT_EP (0x4002A3BC)                                                  */
/*       IVT_EX (0x4002A3BC)                                                  */
/*       HSX (0x4002A3BC)                                                     */
/*       BDX (0x4002A3BC)                                                     */
/* Register default value:              0x00000000                            */
#define MIERRCNTSEL_IIO_RAS_REG 0x090243BC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 */
typedef union {
  struct {
    UINT32 cfg_reg_par : 1;
    /* cfg_reg_par - Bits[0:0], RW, default = 1'b0 
       Config Register par Count Select
     */
    UINT32 smbus_port_sts : 1;
    /* smbus_port_sts - Bits[1:1], RW, default = 1'b0 
       This bit has no effect.
     */
    UINT32 jtag_tap_sts : 1;
    /* jtag_tap_sts - Bits[2:2], RW, default = 1'b0 
       JTAG TAP Status Count Select
     */
    UINT32 vpp_err_sts : 1;
    /* vpp_err_sts - Bits[3:3], RW, default = 1'b0 
       VPP Error Status Count Select.
     */
    UINT32 dfx_inj_err : 1;
    /* dfx_inj_err - Bits[4:4], RW, default = 1'b0 
       DFx Injection Error Count Select
     */
    UINT32 rsvd : 27;
    /* rsvd - Bits[31:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MIERRCNTSEL_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MIERRCNT_IIO_RAS_REG supported on:                                         */
/*       IVT_EP (0x1002A3C0)                                                  */
/*       IVT_EX (0x1002A3C0)                                                  */
/*       HSX (0x1002A3C0)                                                     */
/*       BDX (0x1002A3C0)                                                     */
/* Register default value:              0x00                                  */
#define MIERRCNT_IIO_RAS_REG 0x090213C0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * Miscellaneous Error Count.
 */
typedef union {
  struct {
    UINT8 errcnt : 7;
    /* errcnt - Bits[6:0], RW1CS, default = 7'b0000000 
       This counter accumulates errors that occur when the associated error type is 
       selected in the ERRCNTSEL register. 
       
       Notes:
       This register is cleared by writing 7Fh.
       Maximum counter available is 127d (7Fh).
     */
    UINT8 errovflow : 1;
    /* errovflow - Bits[7:7], RW1CS, default = 1'b0 
       0: No overflow occurred
       1: Error overflow. The error count may not be valid.
     */
  } Bits;
  UINT8 Data;
} MIERRCNT_IIO_RAS_STRUCT;
#endif /* ASM_INC */


/* MCTPSAD_N0_IIO_RAS_REG supported on:                                       */
/*       HSX (0x4002A400)                                                     */
/*       BDX (0x4002A400)                                                     */
/* Register default value:              0x00000000                            */
#define MCTPSAD_N0_IIO_RAS_REG 0x09024400

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x400
 */
typedef union {
  struct {
    UINT32 enable : 1;
    /* enable - Bits[0:0], RW_LB, default = 1'b0 
       If 0, the SAD is not valid and all MCTPs will be routed locally
       If 1, MCTP over Intel QPI is enabled
     */
    UINT32 num_bus : 2;
    /* num_bus - Bits[2:1], RW_LB, default = 2'b00 
       00: MaxBusNumber = 255 Use bits 7:5 of the target bus number as the index into 
       the TARGET_NID array. 
       01: MaxBusNumber = 127. Use bits 6:4 of the target bus number as the index into 
       the TARGET_NID array. 
       10: MaxBusNumber = 63. Use bits 5:3 of the target bus number as the index into 
       the TARGET_NID array. 
       11: Reserved
     */
    UINT32 nid0 : 5;
    /* nid0 - Bits[7:3], RW_LB, default = 5'b00000 
       NID of target socket0
     */
    UINT32 rsvd_8 : 1;
    /* rsvd_8 - Bits[8:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 nid1 : 5;
    /* nid1 - Bits[13:9], RW_LB, default = 5'b00000 
       NID of target socket1
     */
    UINT32 rsvd_14 : 1;
    /* rsvd_14 - Bits[14:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 nid2 : 5;
    /* nid2 - Bits[19:15], RW_LB, default = 5'b00000 
       NID of target socket2
     */
    UINT32 rsvd_20 : 1;
    /* rsvd_20 - Bits[20:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 nid3 : 5;
    /* nid3 - Bits[25:21], RW_LB, default = 5'b00000 
       NID of target socket3
     */
    UINT32 rsvd_26 : 1;
    /* rsvd_26 - Bits[26:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 nid4 : 5;
    /* nid4 - Bits[31:27], RW_LB, default = 5'b00000 
       NID of target socket4
     */
  } Bits;
  UINT32 Data;
} MCTPSAD_N0_IIO_RAS_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* MCTPSAD_N1_IIO_RAS_REG supported on:                                       */
/*       HSX (0x4002A404)                                                     */
/*       BDX (0x4002A404)                                                     */
/* Register default value:              0x00000000                            */
#define MCTPSAD_N1_IIO_RAS_REG 0x09024404

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.2.CFG.xml.
 * generated by critter 05_2_0x400
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 1;
    /* rsvd_0 - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 nid5 : 5;
    /* nid5 - Bits[5:1], RW_LB, default = 5'b00000 
       NID of target socket5
     */
    UINT32 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 nid6 : 5;
    /* nid6 - Bits[11:7], RW_LB, default = 5'b00000 
       NID of target socket6
     */
    UINT32 rsvd_12 : 1;
    /* rsvd_12 - Bits[12:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 nid7 : 5;
    /* nid7 - Bits[17:13], RW_LB, default = 5'b00000 
       NID of target socket7
     */
    UINT32 rsvd_18 : 2;
    /* rsvd_18 - Bits[19:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rc_nid : 3;
    /* rc_nid - Bits[22:20], RW_LB, default = 3'b000 
       Route to RC target NID, implemented as an index into the target NID structure;
       000 = Target NID 0
       001 = Target NID 1
       010 = Target NID 2
       011 = Target NID 3
       100 = Target NID 4
       101 = Target NID 5
       110 = Target NID 6
       111 = Target NID 7
     */
    UINT32 rc_local : 1;
    /* rc_local - Bits[23:23], RW_LB, default = 1'b0 
       When set to 1, indicates the local socket is the RC NID. If local socket is the 
       RC NID, then the Route to RC MCTPs originating from the local IIO will be routed 
       to DMI and not sent on the ring. 
       Default 0.
     */
    UINT32 brd_list : 8;
    /* brd_list - Bits[31:24], RW_LB, default = 8'b00000000 
       Broadcast list, bit mapped into each of 8 target NID locations.
       Bit 56 = Target NID 0 if set to 1
       Bit 57 = Target NID 1 if set to 1
       Bit 58 = Target NID 2 if set to 1
       Bit 59 = Target NID 3 if set to 1
       Bit 60 = Target NID 4 if set to 1
       Bit 61 = Target NID 5 if set to 1
       Bit 62 = Target NID 6 if set to 1
       Bit 63 = Target NID 7 if set to 1
       
       The broadcast list is only valid on the socket attached to the MCTP bus owner. 
       There is only 1 MCTP bus owner per PCIe bus segment. For other sockets, it 
       should be cleared. 
       For the MCTP bus owner socket, its own Target NID should be cleared so it 
       doesn't broadcast traffic through the ring to itself. 
     */
  } Bits;
  UINT32 Data;
} MCTPSAD_N1_IIO_RAS_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


#endif /* IIO_RAS_h */
